From Process Corners to Statistical Circuit Design Methodology: Opportunities and Challenges von Dongaonkar, Sourabh, Mudanai, Sivakumar P., Giles, Martin D.

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Mechanism of Long-Channel Drain-Induced Barrier Lowering in Halo MOSFETs von Roy, A S, Mudanai, S P, Stettler, M

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Compact Modeling of Magnetic Tunneling Junctions von Roy, Ananda S., Sarkar, Angik, Mudanai, Sivakumar P.

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Compact Model for Ultrathin Low Electron Effective Mass Double Gate MOSFET von Roy, Ananda S., Mudanai, Sivakumar P., Basu, Dipanjan, Stettler, Mark A.

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Compressive Uniaxial Stress Bandstructure Engineering for Transferred-Hole Devices von Kotlyar, Roza, Giles, Martin D, Mudanai, Sivakumar P, Kuhn, Kelin J, Cea, Stephen M, Linton, Thomas D, Pillarisetty, Ravi

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An Improved Flicker Noise Model for Circuit Simulations von Roy, Ananda S., Sungwon Kim, Mudanai, Sivakumar P.

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A novel Si/SiGe heterojunction pMOSFET with reduced short-channel effects and enhanced drive current von Qiqing Ouyang, Xiangdong Chen, Mudanai, S.P., Xin Wang, Kencke, D.L., Tasch, A.F., Register, L.F., Banerjee, S.K.

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Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT ∼ 1 nm) SiO2 and high-κ gate stacks von FEI LI, MUDANAI, Sivakumar P, FAN, Yang-Yu, REGISTER, Leonard Franklin, BANERJEE, Sanjay K

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Junctionless accumulation-mode devices on prominent architectures, and methods of making same von RIOS RAFAEL, RAKSHIT TITASH, MUDANAI SIVAKUMAR P, CAPPELLANI ANNALISA, KUHN KELIN J

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JUNCTIONLESS ACCUMULATION-MODE DEVICES ON PROMINENT ARCHITECTURES, AND METHODS OF MAKING SAME von RIOS RAFAEL, RAKSHIT TITASH, MUDANAI SIVAKUMAR P, CAPPELLANI ANNALISA, KUHN KELIN J

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METHOD OF FABRICATING A MOSFET TRANSISTOR HAVING AN ANTI-HALO FOR MODIFYING NARROW WIDTH DEVICE PERFORMANCE von LINDERT, NICK, TYAGI, SUNIT, SHAHEED, M., REAZ, MUDANAI, SIVAKUMAR, P, CURELLO, GIUSEPPE, PIPES, LEONARD, C

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Method of fabricating a MOSFET transistor having an anti-halo for modifying narrow width device performance von TYAGI SUNIT, PIPES LEONARD C, SHAHEED M. R, CURELLO GIUSEPPE, MUDANAI SIVAKUMAR P, LINDERT NICK

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Quantum mechanical modeling of capacitance-voltage and current-voltage behavior for SiO2 and high-K dielectrics von REGISTER, Leonard F, FAN, Yang-Yu, MUDANAI, Sivakumar P, BANERJEE, Sanjay K

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Method of fabricating a MOSFET transistor having an anti-halo for modifying narrow width device performance von LINDERT, NICK, TYAGI, SUNIT, PIPES, LEONARD C, SHAHEED, REAZ M, CURELLO, GIUSEPPE, MUDANAI, SIVAKUMAR P

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Process Technology Variation von Kuhn, K. J., Giles, M. D., Becher, D., Kolar, P., Kornfeld, A., Kotlyar, R., Ma, S. T., Maheshwari, A., Mudanai, S.

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Analytical Modeling of Output Conductance in Long-Channel Halo-Doped MOSFETs von Mudanai, S., Wei-Kai Shih, Rios, R., Xuemei Xi, Jung-Hoon Rhew, Kuhn, K., Packan, P.

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An efficient surface potential solution algorithm for compact MOSFET models von Rios, R., Mudanai, S., Wei-Kai Shih, Packan, P.

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A three-transistor threshold voltage model for halo processes von Rios, R., Wei-Kai Shih, Shah, A., Mudanai, S., Packan, P., Sandford, T., Mistry, K.

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Time-domain device noise simulator von O'Mahony, Frank P, Kutuk, Haydar, Casper, Bryan K, Fayneh, Eyal, Mudanai, Sivakumar, Shih, Wei-kai, Fattouh, Farag

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Time-domain device noise simulator von MUDANAI SIVAKUMAR, KUTUK HAYDAR, FATTOUH FARAG, CASPER BRYAN K, FAYNEH EYAL, SHIH WEI-KAI, O'MAHONY FRANK P

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