Digital data processing system with interface adaptor having programmable monitorable control register therein von ORGILL RODNEY H, HEPWORTH EDWARD C, PEDDLE CHARLES I, CARLOW EARL F, MATHYS WILBUR L, BENNETT THOMAS H, WILES MICHAEL F, MENSCH WILLIAM D. JR

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Data direction register for interface adaptor chip von MENSCH, WILLIAM D, PEDDLE, CHARLES, MATHYS, WILBUR L, WILES, MICHAEL F, CARLOW, EARL F

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Integrated circuit microprocessor with parallel binary adder having on-the-fly correction to provide decimal results von MENSCH, JR., WILLIAM D, ORGILL, RODNEY H, MATHYS, WILBUR L, PEDDLE, CHARLES INGERHAM

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Digital data processing system with interface adaptor having programmable, monitorable control register therein von MENSCH, JR., WILLIAM D, ORGILL, RODNEY H, MATHYS, WILBUR L, HEPWORTH, EDWARD C, WILES, MICHAEL F, BENNETT, THOMAS H, CARLOW, EARL F, PEDDLE, CHARLES I

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Valid memory address enable system for a microprocessor system von MENSCH, JR., WILLIAM D, ORGILL, RODNEY H, MATHYS, WILBUR L, HEPWORTH, EDWARD C, WILES, MICHAEL F, BENNETT, THOMAS H, CARLOW, EARL F, PEDDLE, CHARLES I

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Interrupt system for microprocessor system von MENSCH, JR., WILLIAM D, ORGILL, RODNEY H, MATHYS, WILBUR L, HEPWORTH, EDWARD C, WILES, MICHAEL F, BENNETT, THOMAS H, CARLOW, EARL F, PEDDLE, CHARLES I

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Master slave registers for interface adaptor von MENSCH, JR., WILLIAM D, ORGILL, RODNEY H, MATHYS, WILBUR L, HEPWORTH, EDWARD C, WILES, MICHAEL F, BENNETT, THOMAS H, CARLOW, EARL F, PEDDLE, CHARLES I

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