Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure von Xiang Qiu, Marek-Sadowska, Malgorzata, Maly, Wojciech P.

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On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits von Yi-Wei Lin, Marek-Sadowska, Malgorzata, Maly, W P

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Layout Generator for Transistor-Level High-Density Regular Circuits von Yi-Wei Lin, Marek-Sadowska, M., Maly, W.P.

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2.5-dimensional VLSI system integration von Yangdong Deng, Maly, W.P.

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Evaluating yield and testing impact of sub-wavelength lithography von Wing Chiu Tam, Blanton, R D, Maly, Wojciech P

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Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips von Xiang Qiu, Marek-Sadowska, Malgorzata, Maly, Wojciech P.

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Realizing and and or Functions With Single Vertical-Slit Field-Effect Transistor von Kamath, A., Zhixian Chen, Nansheng Shen, Singh, N., Lo, G. Q., Dim-Lee Kwong, Kasprowicz, D., Pfitzner, A., Maly, W.

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IC design in high-cost nanometer-technologies era von Maly, Wojciech

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Limitations and challenges of computer-aided design technology for CMOS VLSI von Bryant, R.E., Kwang-Ting Cheng, Kahng, A.B., Keutzer, K., Maly, W., Newton, R., Pileggi, L., Rabaey, J.M., Sangiovanni-Vincentelli, A.

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Computer-aided design for VLSI circuit manufacturability von Maly, W.

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Is there always performance overhead for regular fabric? von Yi-Wei Lin, Marek-Sadowska, M., Maly, W., Pfitzner, A., Kasprowicz, D.

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Adder circuits with transistors using independently controlled gates von Weis, M., Pfitzner, A., Kasprowicz, D., Emling, R., Maly, W., Schmitt-Landsiedel, D.

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Stacked 3-dimensional 6T SRAM cell with independent double gate transistors von Weis, M., Pfitzner, A., Kasprowicz, D., Emling, R., Fischer, T., Henzler, S., Maly, W., Schmitt-Landsiedel, D.

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Integrated circuit device, system, and method of fabrication von Maly Wojciech P

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Current signatures: application von Gattiker, A.E., Maly, W.

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Integrated circuit device, system, and method of fabrication von MALY WOJCIECH P

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Design of ICs applying built-in current testing von Maly, Wojciech, Patyra, Marek

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Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring von Chen, J.T., Khare, J., Walker, K., Shaikh, S., Rajski, J., Maly, W.

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Built-in current testing von Maly, W., Patyra, M.

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Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits von Maly, W.

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