Analysis of resistive defects on a foundry 8T SRAM-based IMC architecture von Ammoura, L., Flottes, M.-L., Girard, P., Noel, J.-P., Virazel, A.

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Assessing body built-in current sensors for detection of multiple transient faults von Viera, R.A.C., Dutertre, J.-M., Flottes, M.-L., Potin, O., Natale, G. Di, Rouzeyre, B., Bastos, R. Possamai

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Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection von Dutertre, J.M., Possamai Bastos, R., Potin, O., Flottes, M.L., Rouzeyre, B., Di Natale, G.

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Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS von Dutertre, J.M., Possamai Bastos, R., Potin, O., Flottes, M.L., Rouzeyre, B., Di Natale, G., Sarafianos, A.

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A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard von Di Natale, G., Doulcier, M., Flottes, M. L., Rouzeyre, B.

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A bulk built-in sensor for detection of fault attacks von Possamai Bastos, R., Sill Torres, F., Dutertre, J-M, Flottes, M-L, Di Natale, G., Rouzeyre, B.

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Mutation Sampling Technique for the Generation of Structural Test Data von Scholive, M., Beroulle, V., Robach, C., Flottes, M. L., Rouzeyre, B.

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A Unified DFT Approach for BIST and External Test von Flottes, M-l, Landrault, C, Petitqueux, A

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A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults von Possamai Bastos, R., Sill Torres, F., Dutertre, J.-M, Flottes, M.-L, Di Natale, G., Rouzeyre, B.

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Design for sequential testability: an internal state reseeding approach for 100 % fault coverage von Flottes, M.L., Landrault, C., Petitqueux, A.

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Scan design and secure chip [secure IC testing] von Hely, D., Flottes, M.-L., Bancel, F., Rouzeyre, B., Berard, N., Renovell, M.

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A simple and effective compression scheme for test pins reduction von Flottes, M.-L., Poirier, R., Rouzeyre, B.

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Self-Test Techniques for Crypto-Devices von Di Natale, G., Doulcier, M., Flottes, M.-L., Rouzeyre, B.

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A heuristic for test scheduling at system level von Flottes, M.-L., Pouget, J., Rouzeyre, B.

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An arithmetic structure for test data horizontal compression von Flottes, M.-L., Poirier, R., Rouzeyre, B.

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An efficient approach to SoC wrapper design, TAM configuration and test scheduling von Pouget, J., Larsson, E., Peng, Z., Flottes, M.-L., Rouzeyre, B.

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A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis von Berthelot, D, Flottes, Ml, Rouzeyre, B

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BISTing data paths at behavioral level von Berthelot, D., Flottes, M.-L., Ronzeyre, B.

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Remote Labs for Industrial IC Testing von Pradarelli, B., Latorre, L., Flottes, M.-L., Bertrand, Y., Nouet, P.

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Improving Datapath Testability by Modifying Controller Specification von Flottes, M. L., Rouzeyre, B., Volpe, L.

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