A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits von Wali, I., Deveautour, B., Virazel, Arnaud, Bosio, A., Girard, P., Sonza Reorda, M.

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Evaluating the radiation sensitivity of GPGPU caches: New algorithms and experimental results von Sabena, D., Sonza Reorda, M., Sterpone, L., Rech, P., Carro, L.

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A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores von Wali, I., Virazel, Arnaud, Bosio, A., Girard, P., Pravossoudovitch, S., Reorda, M. Sonza

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On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs von Kastensmidt, F. Lima, Sterpone, L., Carro, L., Reorda, M. Sonza

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On the use of embedded debug features for permanent and transient fault resilience in microprocessors von Portela-Garcia, M., Grosso, M., Gallardo-Campos, M., Sonza Reorda, M., Entrena, L., Garcia-Valderas, M., Lopez-Ongil, C.

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A Functional Approach for Testing the Reorder Buffer Memory von Di Carlo, S., Gaudesi, M., Sanchez, E., Sonza Reorda, M.

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A Hybrid Approach for Detection and Correction of Transient Faults in SoCs von Bernardi, P., Bolzani Poehls, L., Grosso, M., Sonza Reorda, M.

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Software-Based Hardening Strategies for Neutron Sensitive FFT Algorithms on GPUs von Pilla, L. L., Rech, P., Silvestri, F., Frost, C., Navaux, P. O. A., Sonza Reorda, M., Carro, L.

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A New Hybrid Nonintrusive Error-Detection Technique Using Dual Control-Flow Monitoring von Parra, L., Lindoso, A., Portela-Garcia, M., Entrena, L., Du, B., Sonza Reorda, M., Sterpone, L.

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Software-Based Testing for System Peripherals von Grosso, M., Perez Holguin, W. J., Sanchez, E., Sonza Reorda, M., Tonda, A., Velasco Medina, J.

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Observability solutions for in-field functional test of processor-based systems: A survey and quantitative test case evaluation von Perez Acle, J., Cantoro, R., Sanchez, E., Sonza Reorda, M., Squillero, G.

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Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs von Sterpone, L., Sonza Reorda, M., Violante, M., Kastensmidt, F. Lima, Carro, L.

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A System-layer Infrastructure for SoC Diagnosis von Bernardi, P., Grosso, M., Rebaudengo, M., Sonza Reorda, M.

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On-line functionally untestable fault identification in embedded processor cores von Bernardi, P., Bonazza, M., Sanchez, E., Sonza Reorda, M., Ballan, O.

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Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test von de Carvalho, M., Bernardi, P., Sanchez, E., Reorda, M. Sonza, Ballan, O.

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Exploiting circuit emulation for fast hardness evaluation von Civera, P., Macchiarulo, L., Rebaudengo, M., Reorda, M.S., Violante, M.

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Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors von Cheynet, P., Nicolescu, B., Velazco, R., Rebaudengo, M., Sonza Reorda, M., Violante, M.

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Soft-error detection using control flow assertions von Goloubeva, O., Rebaudengo, M., Sonza Reorda, M., Violante, M.

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A programmable BIST for DRAM testing and diagnosis von Bernardi, P, Grosso, M, Reorda, M S, Zhang, Y

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Evaluating the effects of transient faults on vehicle dynamic performance in automotive systems von Corno, F., Esposito, F., Sonza Reorda, M., Tosato, S.

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