First Steps in Creating Online Testable Reversible Sequential Circuits von Khan, Mozammel H. A., Rice, Jacqueline E.

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Automatic tool for test set generation and DfT assessment in analog circuits von Zilch, Lucas B., Lubaszewski, Marcelo S., Balen, Tiago R.

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AN ENGAGED UNIVERSITY: RESCUING SMEs DURING THE COVID-19 CRISIS von BRAUNER, DANIELA FRANCISCO, REICHERT, FERNANDA MACIEL, JANISSEK-MUNIZ, RAQUEL, ZEN, AURORA CARNEIRO, MENEZES, DANIELA CALLEGARO DE, CLOSS, LISIANE QUADRADO, CARRARO, WENDY BEATRIZ WITT HADDAD, RUPPENTHAL, CARLA SIMONE, MÜLLER, FERNANDA MARIA, LUBASZEWSKI, MARCELO SOARES, RHODEN, MARISA IGNEZ S.

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A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms von Amory, Alexandre M., Lazzari, Cristiano, Lubaszewski, Marcelo S., Moraes, Fernando G.

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A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips von Charif, Amir, Coelho, Alexandre, Zergainoh, Nacer-Eddine, Nicolaidis, Michael

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TID in a Switched-Capacitor FPAA: Degradation and Partial Inactivity Windows Due to Compensating Effects in MOS Transistors von Balen, T. R., Vaz, R. G., Cardoso, G. S., Goncalez, O. L., Lubaszewski, M. S.

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A Discrete Event System Approach to Online Testing of Speed Independent Circuits von Biswal, P. K., Mishra, K., Biswas, S., Kapoor, H. K.

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VLSI Architectures for Image Interpolation: A Survey von Moses, C. John, Selvathi, D., Sophia, V. M. Anne

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High Throughput Pseudorandom Number Generator Based on Variable Argument Unified Hyperchaos von Wang, Kaiyu, Yan, Qingxin, Yu, Shihua, Qi, Xianwei, Zhou, Yudi, Tang, Zhenan

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Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing von Saponara, Sergio, Fanucci, Luca

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A Pull-in Based Test Mechanism for Device Diagnostic and Process Characterization von Rocha, L. A., Mol, L., Cretu, E., Wolffenbuttel, R. F., Machado da Silva, J.

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UNIVERSIDADE ENGAJADA: RESGATANDO PMES NA CRISE DA COVID-19 von Brauner, Daniela Francisco, Reichert, Fernanda Maciel, Janissek-Muniz, Raquel, Zen, Aurora Carneiro, De Menezes, Daniela Callegaro, Closs, Lisiane Quadrado, Carraro, Wendy Beatriz Witt Haddad, Ruppenthal, Carla Simone, Müller, Fernanda Maria, Lubaszewski, Marcelo Soares, Rhoden, Marisa Ignez S

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Simple Evaluation of the Nonlinearity Signature of an ADC Using a Spectral Approach von Peralías, E. J., Jalón, M. A., Rueda, A.

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Selected Papers from the International Mixed Signals Testing and GHz/Gbps Test Workshop von Kaminska, Bozena, Lubaszewski, Marcelo, Machado da Silva, José

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A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip von Cota, E., Kastensmidt, F.L., Cassel, M., Herve, M., Almeida, P., Meirelles, P., Amory, A., Lubaszewski, M.

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Exploring design diversity redundancy to improve resilience in mixed-signal systems von Chenet, Cristiano P., Tambara, Lucas A., de Borges, Gabriel M., Kastensmidt, Fernanda, Lubaszewski, Marcelo S., Balen, Tiago R.

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A Tool for Single-Fault Diagnosis in Linear Analog Circuits with Tolerance Using the T-Vector Approach von Soares Augusto, José A., Beltrán Almeida, Carlos

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Can Functional Test Achieve Low-cost Full Coverage of NoC Faults? von Lubaszewski, M.

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Functional Test of Mesh-Based NoCs with Deterministic Routing: Integrating the Test of Interconnects and Routers von Hervé, Marcos Barcellos, Moraes, Marcelo, Almeida, Pedro, Lubaszewski, Marcelo, Kastensmidt, Fernanda Lima, Cota, Érika

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Reusing an on-chip network for the test of core-based systems von Cota, Erika, Carro, Luigi, Lubaszewski, Marcelo

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