Reliability study of 3D IC packaging based on through-silicon interposer (TSI) and silicon-less interconnection technology (SLIT) using finite element analysis von Che, Fa Xing, Zhang, Xiaowu, Lin, Jong-Kai

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Stress Analysis and Design Optimization for Low- k Chip With Cu Pillar Interconnection von Che, Fa Xing, Lin, Jong-Kai, Au, Keng Yuen, Hsiao, Hsiang-Yao, Zhang, Xiaowu

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Failure Morphology After Drop Impact Test of Ball Grid Array (BGA) Package With Lead-Free Sn-3.8Ag-0.7Cu and Eutectic SnPb Solders von Jin-Wook Jang, De Silva, A.P., Drye, J.E., Post, S.L., Owens, N.L., Jong-Kai Lin, Frear, D.R.

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Spalling of Cu3Sn intermetallics in high-lead 95Pb5Sn solder bumps on Cu under bump metallization during solid-state annealing von Jang, Jin-Wook, Ramanathan, Lakshmi N., Lin, Jong-Kai, Frear, Darrel R.

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Squeegee bump technology von Jong-Kai Lin, Treliant Fang, Bajaj, R.

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Characterization of lead-free solders and under bump metallurgies for flip-chip package von Jong-Kai Lin, De Silva, A., Frear, D., Guo, Y., Hayes, S., Jin-Wook Jang, Li, L., Mitchell, D., Yeung, B., Zhang, C.

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Interfacial reaction of eutectic AuSi solder with Si (100) and Si (111) surfaces von Jang, Jin-Wook, Hayes, Scott, Lin, Jong-Kai, Frear, Darrel R.

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Electromigration studies of lead-free solder balls used for wafer-level packaging von Hau-Riege, Christine, Zang, Ricky, You-Wen Yau, Yadav, Praveen, Keser, Beth, Jong-Kai Lin

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Heterogeneous 2.5D integration on through silicon interposer von Zhang, Xiaowu, Lin, Jong Kai, Wickramanayaka, Sunil, Zhang, Songbai, Weerasekera, Roshan, Dutta, Rahul, Chang, Ka Fai, Chui, King-Jien, Li, Hong Yu, Wee Ho, David Soon, Ding, Liang, Katti, Guruprasad, Bhattacharya, Suryanarayana, Kwong, Dim-Lee

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Tensile fracture behaviors of solid-state-annealed eutectic SnPb and lead-free solder flip chip bumps von Jang, Jin-Wook, De Silva, Ananda P., Lin, Jong-Kai, Frear, Darrel R.

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Design analysis of an electroless plating bath using CFD technique von Lee, T.-Y.T., Jong-Kai Lin

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Design analysis of an electroless plating bath using CFD technique von Lee, Tien-Yu Tom, Lin, Jong-Kai

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Stress Analysis and Design Optimization for Low-[Formula Omitted] Chip With Cu Pillar Interconnection von Che, Fa Xing, Lin, Jong-Kai, Au, Keng Yuen, Hsiao, Hsiang-Yao, Zhang, Xiaowu

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Reliability evaluations of chip interconnect in lead-free solder systems von YIFAN GUO, LIN, Jong-Kai, DE SILVA, Anada

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Conductive polymer bump interconnects von Jong-Kai Lin, Drye, J., Lytle, W., Scharr, T., Subrahmanyan, R., Sharma, R.

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Refeeding syndrome in Southeastern Taiwan:Our experience with 11 cases von Chen, Li-Ju, Chen, Huan-Lin, Bair, Ming-Jong, Wu, Chia-Hsien, Lin, I-Tsung, Lee, Yuan-Kai, Chu, Cheng-Hsin

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Thermal fatigue properties of lead-free solders on Cu and NiP under bump metallurgies von Zhang, C., Jong-Kai Lin, Li Li

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A New Method to Evaluate Thin Film Adhesion von Sharma, Ravi, Lin, Jong-Kai, Drye, James, Lindsey, Scott

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Characterization of lead-free solders and under bump metallurgies for flip-chip package von Jong-Kai Lin, De Silva, A., Frear, D., Yifan Guo, Jin-Wook Jang, Li Li, Mitchell, D., Yeung, B., Zhang, C.

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Characterization of solder joint electromigration for flip chip technology von Jong-Kai Lin, Jin-Wook Jang, White, J.

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