Size Independent pH Sensitivity for Ion Sensitive FinFETs Down to 10 nm Width von Gupta, Mihir, Santermans, Sybren, Veloso, Anabela, Tao, Zheng, Li, Waikin, Hellings, Geert, Lagae, Liesbet, Van Roy, Willem, Martens, Koen

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Size Independent pH Sensitivity for Ion Sensitive FinFETs Down to 10 nm Width von Gupta, Mihir, Santermans, Sybren, Veloso, Anabela, Tao, Zheng, Li, Waikin, Hellings, Geert, Lagae, Liesbet, Van Roy, Willem, Martens, Koen

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A METHOD FOR FORMING AN INTERCONNECT STRUCTURE von Tao, Zheng, Li, Waikin

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Method for Forming an Interconnect Structure von Tao, Zheng, Li, Waikin

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A METHOD FOR FORMING AN INTERCONNECT STRUCTURE von Tao, Zheng, Li, Waikin

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(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs von Veloso, Anabela, Paraschiv, Vasile, Vecchio, Emma, Devriendt, Katia, Li, Waikin, Simoen, Eddy, Chan, B. T., Tao, Zheng, Rosseel, Erik, Loo, Roger, Milenin, Alexey P., Kunert, Bernardette, Teugels, Lieve, Sebaai, Farid, Lorant, Christophe, van Dorp, Dennis, Altamirano-Sánchez, Efraín, Brus, Stephan, Marien, Philippe, Fleischmann, Claudia, Melkonyan, Davit, Huynh-Bao, Trong, Eneman, Geert, Hellings, Geert, Sibaja-Hernandez, Arturo, Matagne, Philippe, Waldron, Niamh, Mocuta, Dan, Collaert, Nadine

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Method for Producing a Buried Interconnect Rail of an Integrated Circuit Chip von Tao, Zheng, Li, Waikin

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Contact isolation in semiconductor devices von Tao, Zheng, Li, Waikin, Chan, Boon Teik

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Method for filling a space in a semiconductor von Tao, Zheng, Li, Waikin, Chan, Boon Teik

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Method and Structure for Determining an Overlay Error von Tao, Zheng, Kim, Min-Soo, Li, Waikin

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METHOD FOR FILLING A SPACE IN A SEMICONDUCTOR von Tao, Zheng, Li, Waikin, Chan, Boon Teik

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Contact Isolation in Semiconductor Devices von Tao, Zheng, Li, Waikin, Chan, Boon Teik

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Nanowire-based vertical memory cell array having a metal layer interposed between a common back plate and the nanowires von Pei, Chengwen, Li, Waikin, Wang, Ping-Chuan

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Method for producing a pattern of features by lithography and etching von Halder, Sandip, Li, Waikin, Lazzarino, Frederic, De Simone, Danilo

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Nanowire-based vertical memory cell array having a back plate and nanowire seeds contacting a bit line von Pei, Chengwen, Li, Waikin, Wang, Ping-Chuan

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A METHOD FOR PRODUCING A BURIED INTERCONNECT RAIL OF AN INTEGRATED CIRCUIT CHIP von Li, Mr. Waikin, Tao, Mr. Zheng

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Method for Producing a Pattern of Features by Lithography and Etching von Halder, Sandip, Li, Waikin, Lazzarino, Frederic, De Simone, Danilo

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A METHOD FOR PRODUCING A PATTERN OF FEATURES BY LITHOGRAPHY AND ETCHING von Halder, Sandip, Li, Waikin, Lazzarino, Frederic, De Simone, Danilo

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(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs von Veloso, Anabela, Paraschiv, Vasile, Vecchio, Emma, Devriendt, Katia, Li, Waikin, Simoen, Eddy, Chan, B. T., Tao, Zheng, Rosseel, Erik, Loo, Roger, Milenin, Alexey P., Kunert, Bernardette, Teugels, Lieve, Sebaai, Farid, Lorant, Christophe, van Dorp, Dennis, Altamirano-Sánchez, Efraín, Brus, Stephan, Marien, Philippe, Fleischmann, Claudia, Melkonyan, Davit, Huynh-Bao, Trong, Eneman, Geert, Hellings, Geert, Sibaja-Hernandez, Arturo, Matagne, Philippe, Waldron, Niamh, Mocuta, Dan, Collaert, Nadine

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METHOD AND STRUCTURE FOR DETERMINING AN OVERLAY ERROR von KIM, Min-Soo, LI, Waikin, TAO, Zheng

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