CCALK: (When) CVA6 Cache Associativity Leaks the Key von Martinoli, Valentin, Tourneur, Elouan, Teglia, Yannick, Leveugle, Régis

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High-level fault injection to assess FMEA on critical systems von Roux, Julie, Beroulle, Vincent, Morin-Allory, Katell, Leveugle, Régis, Bossuet, Lilian, Cézilly, Frédéric, Berthoz, Frédéric, Genévrier, Gilles, Cerisier, François

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Dummy operations in scalar multiplication over elliptic curves: A tradeoff between security and performance von Pontie, Simon, Maistri, Paolo, Leveugle, Régis

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CNTFET Modeling and Reconfigurable Logic-Circuit Design von O'Connor, I., Liu Junchen, Gaffiot, F., Pregaldiny, F., Lallement, C., Maneux, C., Goguet, J., Fregonese, S., Zimmer, T., Anghel, L., Trong-Trinh Dang, Leveugle, R.

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Understanding the link between complex digital devices Soft Error Rate and the running software von Noizette, Luc, Miller, Florent, Colladant, Thierry, Helen, Youri, Leveugle, Regis

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Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic von Monnet, Y., Renaudin, M., Leveugle, R.

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Double-Data-Rate Computation as a Countermeasure against Fault Analysis von Maistri, P., Leveugle, R.

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Hardware Support for Security in the Internet of Things: From Lightweight Countermeasures to Accelerated Homomorphic Encryption von Leveugle, Régis, Mkhinini, Asma, Maistri, Paolo

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Forecasting the Effects of Electromagnetic Fault Injections on Embedded Cryptosystems von Alberto, Diego, Maistri, Paolo, Leveugle, Régis

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Hardware Acceleration and Approximation of CNN Computations: Case Study on an Integer Version of LeNet von Leveugle, Régis, Cogney, Arthur, Gah El Hilal, Ahmed Baba, Lailler, Tristan, Pieau, Maxime

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Early Analysis of Fault-based Attack Effects in Secure Circuits von Leveugle, R.

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Case Study of a Fault Attack on Asynchronous DES Crypto-Processors von Monnet, Yannick, Renaudin, Marc, Leveugle, Régis, Clavier, Christophe, Moitrel, Pascal

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A New Critical Variable Analysis in Processor-Based Systems von Bergaoui, Salma, Vanhauwaert, Pierre, Leveugle, Regis

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Analysis of laser-induced errors: RTL fault models versus layout locality characteristics von Papadimitriou, Athanasios, Hély, David, Beroulle, Vincent, Maistri, Paolo, Leveugle, Regis

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Experimental Assessment of Cache Memory Soft Error Rate Prediction Technique von Houssany, Sabrine, Guibbaud, Nicolas, Bougerol, Antonin, Leveugle, Regis, Santini, Thomas, Miller, Florent

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A Highly Flexible Hardened RTL Processor Core Based on LEON2 von Portolan, M., Leveugle, R.

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Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA von Canivet, G., Maistri, P., Leveugle, R., Clédière, J., Valette, F., Renaudin, M.

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Using run-time reconfiguration for fault injection in hardware prototypes von Antoni, L., Leveugle, R., Feher, B.

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Microprocessor Soft Error Rate Prediction Based on Cache Memory Analysis von Houssany, S., Guibbaud, N., Bougerol, A., Leveugle, R., Miller, F., Buard, N.

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Experimental Demonstration of Pattern Influence on DRAM SEU and SEFI Radiation Sensitivities von Bougerol, A, Miller, F, Guibbaud, N, Leveugle, R, Carriere, T, Buard, N

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