Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization von Rai, Shubham, Neto, Walter Lau, Miyasaka, Yukio, Zhang, Xinpei, Yu, Mingfei, Fujita, Qingyang Yi Masahiro, Manske, Guilherme B, Pontes, Matheus F, Junior, Leomar S. da Rosa, de Aguiar, Marilton S, Butzen, Paulo F, Chien, Po-Chun, Huang, Yu-Shan, Wang, Hoa-Ren, Jiang, Jie-Hong R, Gu, Jiaqi, Zhao, Zheng, Jiang, Zixuan, Pan, David Z, de Abreu, Brunno A, Campos, Isac de Souza, Berndt, Augusto, Meinhardt, Cristina, Carvalho, Jonata T, Grellert, Mateus, Bampi, Sergio, Lohana, Aditya, Kumar, Akash, Zeng, Wei, Davoodi, Azadeh, Topaloglu, Rasit O, Zhou, Yuan, Dotzel, Jordan, Zhang, Yichi, Wang, Hanyu, Zhang, Zhiru, Tenace, Valerio, Gaillardon, Pierre-Emmanuel, Mishchenko, Alan, Chatterjee, Satrajit

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Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization von Rai, Shubham, Walter Lau Neto, Miyasaka, Yukio, Zhang, Xinpei, Yu, Mingfei, Qingyang Yi Masahiro Fujita, Manske, Guilherme B, Pontes, Matheus F, Leomar S da Rosa Junior, de Aguiar, Marilton S, Butzen, Paulo F, Po-Chun Chien, Yu-Shan, Huang, Hoa-Ren, Wang, Jiang, Jie-Hong R, Gu, Jiaqi, Zhao, Zheng, Jiang, Zixuan, Pan, David Z, de Abreu, Brunno A, Isac de Souza Campos, Berndt, Augusto, Meinhardt, Cristina, Carvalho, Jonata T, Mateus Grellert, Bampi, Sergio, Lohana, Aditya, Kumar, Akash, Zeng, Wei, Davoodi, Azadeh, Topaloglu, Rasit O, Zhou, Yuan, Dotzel, Jordan, Zhang, Yichi, Wang, Hanyu, Zhang, Zhiru, Tenace, Valerio, Pierre-Emmanuel Gaillardon, Mishchenko, Alan, Chatterjee, Satrajit

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Transistor-level optimization of CMOS complex gates von Possani, V. N., Marques, F. S., da Rosa Junior, L. S., Callegaro, V., Reis, A. I., Ribas, R. P.

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A Media Processing Implementation Using Libvlc for the Ginga Middleware von Trojahn, Tiago H., Goncalves, Juliano L., Mattos, Julio C. B., Da Rosa Junior, Leomar S., Agostini, Luciano V.

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Migortho: A Design Automation Flow for QCA Circuits von Domingues Junior, Julio Saracol, Junior, Leomar Soares da Rosa, Marques, Felipe de Souza

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