Validity and reliability of Kinect skeleton for measuring shoulder joint angles: a feasibility study von Huber, M.E, Seitz, A.L, Leeser, M, Sternad, D

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Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA von Noseworthy, J., Leeser, M.

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Hardware Specification, Verification and Synthesis: Mathematical Aspects: Mathematical Sciences Institute Workshop Cornell University, Ithaca, New York, USA July 5–7, 1989 Proceedi... von Leeser, Miriam, Brown, Geoffrey

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Vforce: An Extensible Framework for Reconfigurable Supercomputing von Moore, N., Conti, A., Leeser, M., King, L.S.

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HML, a novel hardware description language and its translation to VHDL von Yanbing Li, Leeser, M.

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Division and square root: choosing the right implementation von Soderquist, P., Leeser, M.

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Enabling MPEG-2 video playback in embedded systems through improved data cache efficiency von Soderquist, P., Leeser, M., Rojas, J.-C.

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A data-centric approach to high-level synthesis von Tarafdar, S., Leeser, M.

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Minimum Energy Analysis and Experimental Verification of a Latch-Based Subthreshold FPGA von Grossmann, P. J., Leeser, M. E., Onabajo, M.

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Acknowledgment to special issue reviewers von Kaeli, D.R., Leeser, M.

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Design and analysis of a dynamically reconfigurable three-dimensional FPGA von Chiricescu, S., Leeser, M., Vai, M.M.

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Verifying a logic-synthesis algorithm and implementation: a case study in software verification von Aagaard, M., Leeser, M.

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Accurate Power Estimation for Sequential CMOS Circuits Using Graph-based Methods von Leeser, Miriam, Ohm, Valerie

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Area and performance tradeoffs in floating-point divide and square-root implementations von SODERQUIST, P, LEESER, M

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PBS: proven Boolean simplification von Aagaard, M., Leeser, M.

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Reasoning about the function and timing of integrated circuits with interval temporal logic von Leeser, M.E.

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Run-time execution of reconfigurable hardware in a Java environment von Smith King, L.A., Quinn, H., Leeser, M., Galatopoullos, D., Manolakos, E.

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Design tradeoffs in a hardware implementation of the k-means clustering algorithm von Leeser, M., Theiler, J., Estlick, M., Szymanski, J.J.

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Memory traffic and data cache behavior of an MPEG-2 software decoder von Soderquist, P., Leeser, M.

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Verification of a subtractive radix-2 square root algorithm and implementation von Leeser, M., O'Leary, J.

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