3.6 mw low power wireless RF receiver front end using creative current recycle technique von Damodara Venkata Appala Naidu, T., Madhavi, B. K., Lal Kishore, K.

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Electronic Measurements and Instrumentation von Kishore, K. Lal

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Design and performance analysis of digitally controlled multi-mode multi-band power amplifier for Sub-6 GHz applications von Racha, Ganesh, Kishore, K Lal, Kamatham, Yedukondalu, Perumalla, Srinivasa Rao

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FPGA Implementation of 5G NR Primary and Secondary Synchronization von Ramesh Kumar, Aytha, Lal Kishore, K.

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Power Analysis and Optimization Techniques of an 8-bit FIR Filter from RTL through GDSII von Kumar, C Ashok, Madhavi, B K, Kishore, K Lal

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Enhanced Clock Gating Technique for Power Optimization in SRAM and Sequential Circuit von Ashok Kumar, Cheeli, Madhavi, B.K., Kishore, K. Lal

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Multiple Target Detection for High Resolution Doppler Radar von Moinuddin, Mohd Moazzam, Y, Mallikarjuna Reddy, A, Pasha I, Naveed, Syed A, K, Lal Kishore

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Mono-alphabetic Poly-semantic Sequence Design for HRR Target Detection von Moinuddin, Mohd. Moazzam, Reddy. Y, Mallikarjuna, I. A ., Pasha, K., Lal Kishore

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Low Leakage CNTFET SRAM Cells von Somineni, Rajendra Prasad, Madhavi, B.K., Kishore, K. Lal

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Design of a 32nm 7T SRAM Cell based on CNTFET for low power operation von Prasad, S. Rajendra, Madhavi, B. K., Kishore, K. Lal

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Dimensional Dependence of Voltage Coefficient of Resistance (αv) for PMNPT Based Varistors von Narasimham, K. V. N. S. V. P. L., Kishore, K. Lal

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Super Resolution Reconstruction in Mixed Noise Environment von Devi, A Geetha, Madhu, T, Kishore, K Lal

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A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic von Rao, P Prasad, Kishore, K Lal

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Dynamic spectrum management scheme in a smart software radio von Rallapalli, H., Lal Kishore, K.

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A Technique to Reduce Glitch Power during Physical Design Stage for Low Power and Less IR Drop von KumarB.V.P, Vasantha, S. Murthy Sharma, N., Lal Kishore, K.

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Power optimized programmable embedded controller von Kamaraju, M, K Lal Kishore, Tilak, A V N

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Efficient Crosstalk Reduction Technique for Data Bus von Sathish, A, Latha, M Madhavi, Kishore, K Lal

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A Novel Approach to Reduce Leakage Power in GALS System architectures von Rajakumari, A, Murthy Sharma, N S, Kishore, K Lal

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Efficient Switching Activity Reduction Technique for Fault Tolerant Data Bus von Sathish, A, Latha, M Madhavi, Kishore, K Lal

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A technique to eliminate glitch power consumption at physical design stage in CMOS circuits von Kumar, Vasantha B. V. P., Sharma, N. S. Murthy, Kishore, K. Lal, Vivekanand, M., Raju, K. Murthy, Swetha, S. Divya

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