An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors von Loke, A. L. S., Doyle, B. A., Maheshwari, S. K., Fischette, D. M., Wang, C. L., Tin Tin Wee, Fang, E. S.

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A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking von Loke, A.L.S., Barnes, R.K., Wee, T.T., Oshima, M.M., Moore, C.E., Kennedy, R.R., Gilsdorf, M.J.

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An Embedded All-Digital Circuit to Measure PLL Response von Fischette, Dennis M, Loke, Alvin L S, DeSantis, Richard J, Talbot, Gerry R

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Microstructure and reliability of copper interconnects von Changsup Ryu, Kee-Won Kwon, Loke, A.L.S., Haebum Lee, Nogami, T., Dubin, V.M., Kavari, R.A., Ray, G.W., Wong, S.S.

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Kinetics of copper drift in PECVD dielectrics von Loke, A.L.S., Changsup Ryu, Yue, C.P., Cho, J.S.H., Wong, S.S.

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SIS wide-band model extraction methodology for SOI on-chip inductor von Topaloglu, Rasit Onur, Jung-Suk Goo, Loke, Alvin L S, Oshima, Michael M, Sim, Sam Wonsae

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Bridging design and manufacture of analog/mixed-signal circuits in advanced CMOS von Jia Feng, Loke, A. L. S., Tin Tin Wee, Lackey, C. O., Okada, L. A., Schwan, C. T., Mantei, T., Morgan, J. H., Herden, M. M., Cooper, J. G., Zhi-Yuan Wu, Jung-Suk Goo, Xin Li, Icel, A. B., Bair, L. A., Fischette, D. M., Doyle, B. A., Fang, E. S., Leary, B. M., Krishnan, S.

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HYDROGEN-ROBUST SUBMICRON IrOx/Pb(Zr, Ti)O3/Ir CAPACITORS FOR EMBEDDED FERROELECTRIC MEMORY von Sakoda, T, Moise, T S, Summerfelt, S R, Colombo, L, Xing, G, Gilbert, S R

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Electrical leakage at low-K polyimide/TEOS interface von Loke, A.L.S., Wetzel, J.T., Stankus, J.J., Angyal, M.S., Mowry, B.K., Wong, S.S.

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Analog/Mixed-Signal Design in FinFET Technologies von Loke, Alvin L. S., Terzioglu, Esin, Kumar, Albert A., Wee, Tin Tin, Rim, Kern, Yang, Da, Yu, Bo, Ge, Lixin, Sun, Li, Holland, Jonathan L., Lee, Chulkyu, Song, Deqiang, Yang, Sam, Zhu, John, Choi, Jihong, Lakdawala, Hasnain, Chen, Zhiqin, Chen, Wilson J., Dundigal, Sreeker, Knol, Stephen R., Tan, Chiew-Guan, Song, Stanley S. C., Dang, Hai, Drennan, Patrick G., Yuan, Jun, Chidambaram, P. R., Jalilizeinali, Reza, Dillen, Steven J., Kong, Xiaohua, Leary, Burton M.

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Barriers for copper interconnections von Ryu, Changsup, Lee, Haebum, Kwon, Kee-Won, Loke, Alvin L.S, Wong, S. Simon

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Methods and apparatuses for testing a voltage-controlled oscillator (VCO) to verify operation across supply voltage and/or temperature von LOKE ALVIN L.S, GILSDORF MICHAEL J

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Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors von Doyle, B. A., Loke, A. L. S., Maheshwari, S. K., Wang, C. L., Fischette, D. M., Cooper, J. G., Aggarwal, S. K., Wee, T. T., Lackey, C. O., Kedarnath, H. S., Oshima, M. M., Talbot, G. R., Fang, E. S.

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Self-tuning varactor system von LOKE ALVIN L.S, BARNES ROBERT K

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Cross-coupled inductor pair formed in an integrated circuit von LOKE ALVIN L.S, MARTIN ROBERT J, FISHER PHILIP W

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Phase detector system with asynchronous output override von LOKE ALVIN L.S, BARNES ROBERT K, BARNES JAMES O

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DELAY-LOCKED LOOP AND A METHOD OF TESTING A DELAY-LOCKED LOOP von MEIER PETER J, LOKE ALVIN L.S, REARICK JEFFREY R, GILSDORF MICHAEL J

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Delay-locked loop and a method of testing a delay-locked loop von GILSDORF MICHAEL JOSEPH, MEIER PETER J, LOKE ALVIN L.S, REARICK JEFFREY R

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Method and apparatus for biasing a metal-oxide-semiconductor capacitor for capacitive tuning von LOKE ALVIN L.S, CYNKAR THOMAS E, WEE TIN T, BARNES ROBERT K, ARAVE KARI L, PFIESTER JAMES R

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