Design space exploration for 3D architectures von Xie, Yuan, Loh, Gabriel H., Black, Bryan, Bernstein, Kerry

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Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) von Dae Hyun Kim, Athikulwongse, Krit, Healy, Michael B., Hossain, Mohammad M., Moongon Jung, Khorosh, Ilya, Kumar, Gokul, Young-Joon Lee, Lewis, Dean L., Tzu-Wei Lin, Chang Liu, Panth, Shreepad, Pathak, Mohit, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Loh, Gabriel H., Lee, Hsien-Hsin S., Sung Kyu Lim

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3D-Stacked Memory Architectures for Multi-core Processors von Loh, Gabriel H.

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Processor Design in 3D Die-Stacking Technologies von Loh, Gabriel H., Xie, Yuan, Black, Bryan

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Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap von Loh, G., Hill, M. D.

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Achieving Exascale Capabilities through Heterogeneous Computing von Schulte, Michael J., Ignatowski, Mike, Loh, Gabriel H., Beckmann, Bradford M., Brantley, William C., Gurumurthi, Sudhanva, Jayasena, Nuwan, Paul, Indrani, Reinhardt, Steven K., Rodgers, Gregory

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Exploiting Interposer Technologies to Disintegrate and Reintegrate Multicore Processors von Kannan, Ajaykumar, Jerger, Natalie Enright, Loh, Gabriel H.

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3D-Integrated SRAM Components for High-Performance Microprocessors von Puttaswamy, K., Loh, G.H.

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3D Stacked Microprocessor: Are We There Yet? von Loh, Gabriel H, Yuan Xie

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Scalability of 3D-integrated arithmetic units in high-performance microprocessors von Puttaswamyt, Kiran, Loh, Gabriel H.

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Die Stacking (3D) Microarchitecture von Black, Bryan, Annavaram, Murali, Brekelbaum, Ned, DeVale, John, Jiang, Lei, Loh, Gabriel H., McCaule, Don, Morrow, Pat, Nelson, Donald W., Pantuso, Daniel, Reed, Paul, Rupley, Jeff, Shankar, Sadasivan, Shen, John, Webb, Clair

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Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors von Puttaswamy, K., Loh, G.H.

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A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches von Sim, Jaewoong, Loh, Gabriel H., Sridharan, Vilas, O'Connor, Mike

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Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs von Healy, M., Vittes, M., Ekpanyapong, M., Ballapuram, C.S., Sung Kyu Lim, Lee, H.-H.S., Loh, G.H.

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Adaptive Caches: Effective Shaping of Cache Behavior to Workloads von Subramanian, Ranjith, Smaragdakis, Yannis, Loh, Gabriel H.

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Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors von Puttaswamy, K., Loh, G.H.

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Design and optimization of the store vectors memory dependence predictor von Subramaniam, Samantika, Loh, Gabriel H

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Fire-and-Forget: Load/Store Scheduling with No Store Queue at All von Subramaniam, Samantika, Loh, Gabriel H.

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Interconnect Design for Heterogeneous Integration of Chiplets in the AMD Instinct™ MI300X Accelerator von Smith, Alan, Loh, Gabriel H., Naffziger, Samuel, Wuu, John, Kalyanasundharam, Nathan, Chapman, Eric, Swaminathan, Raja, Huang, Tyrone, Jung, Wonjun, Kaganov, Alexander, McIntyre, Hugh, Mangaser, Ramon

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Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems von Ausavarungnirun, R., Chang, Kevin Kai-Wei, Subramanian, L., Loh, G. H., Mutlu, O.

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