Treffer 1 - 15 von 15 für Suche 'LELOUP, Xavier Loic', Suchdauer: 0,74s Treffer weiter einschränken
  1. 1
    SYSTEM FOR PROVIDING A LOW LATENCY AND FAST SWITCHED CASCADED DUAL PHASED LOCK LOOP (PLL) ARCHITECTURE FOR DIE-TO-DIE / SYSTEM-ON-CHIP (SOC) INTERFACES

    SYSTEM FOR PROVIDING A LOW LATENCY AND FAST SWITCHED CASCADED DUAL PHASED LOCK LOOP (PLL) ARCHITECTURE FOR DIE-TO-DIE / SYSTEM-ON-CHIP (SOC) INTERFACES von LELOUP, Xavier Loic, SRINIVAS, Vaishnav, JAGER, Michael David, AVOINNE, Christophe, NAGARAJAN, Mahalingam

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  2. 2
    SYSTEM FOR PROVIDING A LOW LATENCY AND FAST SWITCHED CASCADED DUAL PHASED LOCK LOOP (PLL) ARCHITECTURE FOR DIE-TO-DIE / SYSTEM-ON-CHIP (SOC) INTERFACES

    SYSTEM FOR PROVIDING A LOW LATENCY AND FAST SWITCHED CASCADED DUAL PHASED LOCK LOOP (PLL) ARCHITECTURE FOR DIE-TO-DIE / SYSTEM-ON-CHIP (SOC) INTERFACES von LELOUP, Xavier Loic, SRINIVAS, Vaishnav, JAGER, Michael David, AVOINNE, Christophe, NAGARAJAN, Mahalingam

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  3. 3
    System for providing a low latency and fast switched cascaded dual phased lock loop (PLL) architecture for die-to-die / system-on-chip (SoC) interfaces

    System for providing a low latency and fast switched cascaded dual phased lock loop (PLL) architecture for die-to-die / system-on-chip (SoC) interfaces von Nagarajan, Mahalingam, Avoinne, Christophe, Jager, Michael David, Srinivas, Vaishnav, Leloup, Xavier Loic

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  4. 4
    PACKAGE COMPRISING INTEGRATED DEVICES

    PACKAGE COMPRISING INTEGRATED DEVICES von LELOUP, Xavier Loic, PARK, Joon Young, SRINIVAS, Vaishnav, JAGER, Michael David, PAYNTER, Charles David, AVOINNE, Christophe, NAGARAJAN, Mahalingam, JUNEJA, Nitin

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  5. 5
    PACKAGE COMPRISING INTEGRATED DEVICES

    PACKAGE COMPRISING INTEGRATED DEVICES von LELOUP, Xavier Loic, PARK, Joon Young, SRINIVAS, Vaishnav, JAGER, Michael David, PAYNTER, Charles David, AVOINNE, Christophe, NAGARAJAN, Mahalingam, JUNEJA, Nitin

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  6. 6
    MEMORY WITH SYSTEM ECC

    MEMORY WITH SYSTEM ECC von MOLL, Laurent Rene, CHUN, Dexter Tamio, LELOUP, Xavier Loic, SUH, Jungwon, LO, Michael Hawjing

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  7. 7
    MEMORY WITH DYNAMIC VOLTAGE SCALING

    MEMORY WITH DYNAMIC VOLTAGE SCALING von MOLL, Laurent Rene, CHUN, Dexter Tamio, LELOUP, Xavier Loic, SUH, Jungwon, LO, Michael Hawjing

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  8. 8
    Memory with system ECC

    Memory with system ECC von Suh, Jungwon, Moll, Laurent Rene, Lo, Michael Hawjing, Chun, Dexter Tamio, Leloup, Xavier Loic

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  9. 9
    Memory with dynamic voltage scaling

    Memory with dynamic voltage scaling von Suh, Jungwon, Moll, Laurent Rene, Lo, Michael Hawjing, Chun, Dexter Tamio, Leloup, Xavier Loic

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  10. 10
    MEMORY WITH SYSTEM ECC

    MEMORY WITH SYSTEM ECC von MOLL, Laurent Rene, CHUN, Dexter Tamio, LELOUP, Xavier Loic, SUH, Jungwon, LO, Michael Hawjing

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  11. 11
    MEMORY WITH DYNAMIC VOLTAGE SCALING

    MEMORY WITH DYNAMIC VOLTAGE SCALING von MOLL, Laurent Rene, CHUN, Dexter Tamio, LELOUP, Xavier Loic, SUH, Jungwon, LO, Michael Hawjing

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  12. 12
    MEMORY WITH SYSTEM ECC

    MEMORY WITH SYSTEM ECC von MOLL, Laurent Rene, CHUN, Dexter Tamio, LELOUP, Xavier Loic, SUH, Jungwon, LO, Michael Hawjing

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  13. 13
    MEMORY WITH DYNAMIC VOLTAGE SCALING

    MEMORY WITH DYNAMIC VOLTAGE SCALING von MOLL, Laurent Rene, CHUN, Dexter Tamio, LELOUP, Xavier Loic, SUH, Jungwon, LO, Michael Hawjing

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  14. 14
    Memory with dynamic voltage scaling

    Memory with dynamic voltage scaling von SUH, JUNGWON, LO, MICHAEL HAWJING, MOLL, LAURENT RENE, CHUN, DEXTER TAMIO, LELOUP, XAVIER LOIC

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  15. 15
    Memory with system ECC

    Memory with system ECC von SUH, JUNGWON, LO, MICHAEL HAWJING, MOLL, LAURENT RENE, CHUN, DEXTER TAMIO, LELOUP, XAVIER LOIC

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