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  1. 1
    Single-ended transmission for direct access test mode within a differential input and output circuit

    Single-ended transmission for direct access test mode within a differential input and output circuit von Fang, Wayne, Chan, Andy, Lee, Kuek-Hock

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  2. 2
    Single-ended transmission for direct access test mode within a differential input and output circuit

    Single-ended transmission for direct access test mode within a differential input and output circuit von FANG WAYNE, LEE KUEK-HOCK, CHAN ANDY

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  3. 3
    Single-ended transmission for direct access test mode within a differential input and output circuit

    Single-ended transmission for direct access test mode within a differential input and output circuit von FANG WAYNE, LEE KUEK-HOCK, CHAN ANDY

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  4. 4
    A process independent 800 MB/s DRAM bytewide interface featuring command interleaving and concurrent memory operation

    A process independent 800 MB/s DRAM bytewide interface featuring command interleaving and concurrent memory operation von Griffin, M., Zerbe, J., Chan, A., Jun, Y.-H., Tanaka, Y., Richardson, W., Tsang, G., Ching, M., Portmann, C., Li, Y.-X., Stonecypher, B., Lai, L., Lee, K.H., Lee, V., Stark, D., Modarres, H., Batra, P., Louis-Chandran, J., Privitera, J., Thrush, T., Nickell, B., Yang, J., Hennon, V., Sauve, R.


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