PyCUDA and PyOpenCL: A scripting-based approach to GPU run-time code generation von Klöckner, Andreas, Pinto, Nicolas, Lee, Yunsup, Catanzaro, Bryan, Ivanov, Paul, Fasih, Ahmed

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Chisel: constructing hardware in a Scala embedded language von Bachrach, Jonathan, Vo, Huy, Richards, Brian, Lee, Yunsup, Waterman, Andrew, Avižienis, Rimas, Wawrzynek, John, Asanović, Krste

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An Agile Approach to Building RISC-V Microprocessors von Yunsup Lee, Waterman, Andrew, Cook, Henry, Zimmer, Brian, Keller, Ben, Puggelli, Alberto, Kwak, Jaehwa, Jevtic, Ruzica, Bailey, Stevo, Blagojevic, Milovan, Pi-Feng Chiu, Avizienis, Rimas, Richards, Brian, Bachrach, Jonathan, Patterson, David, Alon, Elad, Nikolic, Bora, Asanovic, Krste

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A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI von Keller, Ben, Cochet, Martin, Zimmer, Brian, Kwak, Jaehwa, Puggelli, Alberto, Yunsup Lee, Blagojevic, Milovan, Bailey, Stevo, Pi-Feng Chiu, Dabbelt, Palmer, Schmidt, Colin, Alon, Elad, Asanovic, Krste, Nikolic, Borivoje

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Biomimetically Reinforced Polyvinyl Alcohol-Based Hybrid Scaffolds for Cartilage Tissue Engineering von Kim, Hwan D, Lee, Yunsup, Kim, Yunhye, Hwang, Yongsung, Hwang, Nathaniel S

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Regulation of lubricin for functional cartilage tissue regeneration: a review von Lee, Yunsup, Choi, Jaehoon, Hwang, Nathaniel S

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SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS von Zimmer, B., Seng Oon Toh, Huy Vo, Yunsup Lee, Thomas, O., Asanovic, K., Nikolic, B.

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Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators von YUNSUP LEE, AVIZIENIS, Rimas, BISHARA, Alex, XIA, Richard, LOCKHART, Derek, BATTEN, Christopher, ASANOVIC, Krste

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Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators von Lee, Yunsup, Avizienis, Rimas, Bishara, Alex, Xia, Richard, Lockhart, Derek, Batten, Christopher, Asanović, Krste

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Single-chip microprocessor that communicates directly using light von Sun, Chen, Wade, Mark T., Lee, Yunsup, Orcutt, Jason S., Alloatti, Luca, Georgas, Michael S., Waterman, Andrew S., Shainline, Jeffrey M., Avizienis, Rimas R., Lin, Sen, Moss, Benjamin R., Kumar, Rajesh, Pavanello, Fabio, Atabaki, Amir H., Cook, Henry M., Ou, Albert J., Leu, Jonathan C., Chen, Yu-Hsin, Asanović, Krste, Ram, Rajeev J., Popović, Miloš A., Stojanović, Vladimir M.

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A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI von Zimmer, Brian, Lee, Yunsup, Puggelli, Alberto, Kwak, Jaehwa, Jevtic, Ruzica, Keller, Ben, Bailey, Steven, Blagojevic, Milovan, Chiu, Pi-Feng, Le, Hanh-Phuc, Chen, Po-Hung, Sutardja, Nicholas, Avizienis, Rimas, Waterman, Andrew, Richards, Brian, Flatresse, Philippe, Alon, Elad, Asanovic, Krste, Nikolic, Borivoje

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Convergence and scalarization for data-parallel architectures von Asanovic, Krste, Keckler, Stephen W., Lee, Yunsup, Krashinsky, Ronny, Grover, Vinod

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RAMP gold: An FPGA-based architecture simulator for multiprocessors von Tan, Zhangxi, Waterman, Andrew, Avizienis, Rimas, Lee, Yunsup, Cook, Henry, Patterson, David, Asanovica, Krste

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Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators von Lee, Yunsup, Avizienis, Rimas, Bishara, Alex, Xia, Richard, Lockhart, Derek, Batten, Christopher, Asanović, Krste

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Efficient, high-quality image contour detection von Catanzaro, Bryan, Su, Bor-Yiing, Sundaram, Narayanan, Lee, Yunsup, Murphy, Mark, Keutzer, Kurt

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Automated microprocessor design von Cave, Michael, Lee, Yunsup

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Automated Microprocessor Design von LEE, Yunsup, CAVE, Michael

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Computer organization and design: the hardware/software interface von Patterson, David A, Hennessy, John L

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INTEGRATED CIRCUITS AS A SERVICE von LEE, Yunsup, CAVE, Michael

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Integrated Circuit Generation Using an Integrated Circuit Shell von Daine, Erik Arthur, Macdonald, Ryan, Lee, Yunsup, Terpstra, Wesley Waylon

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