A 1.2 V Single Event Multinode Upset Tolerant RHSC 12T Memory Cell in 65-nm CMOS von Dohar, Suraj Singh, K., Siddharth R., H., Vasantha M., B., Nithin Kumar Y.

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A 1.2 V, Highly Reliable RHBD 10T SRAM Cell for Aerospace Application von Dohar, Suraj Singh, R. K., Siddharth, M. H., Vasantha, Y. B., Nithin Kumar

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Advances in VLSI and Embedded Systems: Select Proceedings of AVES 2019 von Patel, Zuber, Gupta, Shilpi, Kumar Y. B., Nithin

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An Error Bound Particle Swarm Optimization for Analog Circuit Sizing von Shreeharsha, K. G., Siddharth, R. K., Vasantha, M. H., Kumar, Y. B. Nithin

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N-Parallel Paths-Based D-Latch for High-Speed Applications von Rakhi, R., Siddharth, R. K., Shreeharsha, K. G., Vasantha, M. H., Nithin Kumar, Y. B.

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A Novel Complex Filter Design With Dual Feedback for High Frequency Wireless Receiver Applications von Veerendranath, P. S., Sharma, Vivek, Vasantha, M. H., Kumar, Y. B. Nithin

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Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing von Shreeharsha, K. G., Siddharth, R. K., Vasantha, M. H., Kumar, Y. B. Nithin

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Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic von Raveendran, Sithara, Edavoor, Pranose J., Kumar, Y. B. Nithin, Vasantha, M. H.

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Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications von Manikantta Reddy, K., Vasantha, M.H., Nithin Kumar, Y.B., Keshava Gopal, Ch, Dwivedi, Devesh

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An Approximate Low-Power Lifting Scheme Using Reversible Logic von Raveendran, Sithara, Edavoor, Pranose J., Kumar, Nithin Y. B., Vasantha, M. H.

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A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications von Siddharth, R. K., Jaya Satyanarayana, Y., Nithin Kumar, Y. B., Vasantha, M. H., Bonizzoni, Edoardo

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Design and analysis of multiplier using approximate 4-2 compressor von Manikantta Reddy, Karri, Vasantha, M.H., Nithin Kumar, Y.B., Dwivedi, Devesh

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Design of Approximate Booth Squarer for Error-Tolerant Computing von Manikantta Reddy, K., Vasantha, M. H., Nithin Kumar, Y. B., Dwivedi, Devesh

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A novel tunable bandgap voltage and current reference generation circuit von Kumar, H. Prem Sai, Sharma, Vivek, Kumar, Y. B. Nithin, Vasantha, M. H.

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6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process von Rajkumar Kala, Siddharth, Chandaka, Sushma, Kumar Y. B, Nithin, Moodabettu Harishchandra, Vasantha, Bonizzoni, Edoardo

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0.5 V, 254 μW Second-Order Tunable Biquad Low-Pass Filter with 7.3 fJ FOM Using a Novel Low-Voltage Fully Balanced Current-Mode Circuit von Veerendranath, P. S., Sharma, Vivek, Vasantha, M. H., Nithin Kumar, Y. B.

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Generation of complex impedance for complex filter design using fully balanced current conveyors von Veerendranath, P. S., Sharma, Vivek, Vasantha, M. H., Nithin Kumar, Y. B.

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Two-Path Quadrature Cascaded Band-Pass Sigma-Delta Modulators von Kumar, Nithin Y. B., Bonizzoni, E., Patra, A., Maloberti, F.

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Two-path double delay line based bandpass quadrature ΣΔ modulator von NITHIN KUMAR, Y. B, BONIZZONI, E, PATRA, A, MALOBERTI, F

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Slew-rate and gain enhancement in two stage operational amplifiers von Perez, A.P., Nithin Kumar, Y.B., Bonizzoni, E., Maloberti, F.

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