Design Techniques for a 30-ns Access Time 1.5-V 200-KB Embedded EEPROM Memory von Xu, Yiran, Hu, Jian, Xiao, Jun, Yang, Guangjun, Kong, Weiran

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Low-cost single event double-upset tolerant latch design von Jiang, Jianwei, Xu, Yiran, Ren, Jiangchuan, Zhu, Wenyi, Lin, Dianpeng, Xiao, Jun, Kong, Weiran, Zou, Shichang

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A novel symmetrical split-gate structure for 2-bit per cell flash memory von 方亮 孔蔚然 顾靖 张博 邹世昌

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Enhance the split-gate flash cell performance by partially decoupling the SG oxide thickness from the tunnel oxide thickness von Dong, Yaoqi, Kong, Weiran, Do, Nhan, Wang, Shiuh Luen, Lee, Gabriel

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A comprehensive study of various etch processes for the removal of silicide-block-film in submicron CMOS technologies von Li, Rui, Wang, Jun, Sun, Zhenhai, Dong, Yaoqi, Kong, Weiran, Yu, Liujiang, He, Jun, Cheng, Xiaohua, Wang, Chingdong

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Investigation of charge trapping/de-trapping induced operation lifetime degradation in triple SuperFlash ® memory cell von Cao, Zigui, Zhang, Bo, Zhang, Xiong, Lee, Elton, Kong, Weiran

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Fabrication and optimization of aggressively scaled Dual-Bit/Cell Split-Gate Floating-Gate flash memory cell in 55-nm node technology von Chen, Hualun, Xu, Zhaozhao, Xiong, Wei, Zhang, Jian, Xu, Xiaojun, Wang, Hui, Dang, Yang, Wang, Jinfeng, Song, Wan, Tian, Tian, Liu, Donghua, Qian, Wensheng, Kong, Weiran

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A duplex current‐reused CMOS LNA with complementary derivative superposition technique von Dai, Ruofan, Zheng, Yunlong, He, Jun, Kong, Weiran, Zou, Shichang

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Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance von Yaoqi, Dong, Weiran, Kong, Do, Nhan, Shiuh-Luen, Wang, Gabriel, Lee

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Device scaling considerations for sub-90-nm 2-bit/cell split-gate flash memory cell von Xu, Zhaozhao, Liu, Donghua, Hu, Jun, Chen, Wenjie, Qian, Wensheng, Kong, Weiran, Zou, Shichang

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Investigation of read disturb in split-gate memory and its feasible solution von Zhu, Wenyi, Li, Binghan, Yu, Tao, Kong, Weiran, Zou, Shichan

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A 280-KBytes Twin-Bit-Cell Embedded NOR Flash Memory With a Novel Sensing Current Protection Enhanced Technique and High-Voltage Generating Systems von Xu, Yiran, Zhu, Wenyi, Xiao, Jun, Yang, Guangjun, Hu, Jian, Zhang, Shengbo, Huang, Mingyong, Kong, Weiran, Zou, Shichang

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A high gain and high linearity current-reused CMOS LNA using modified derivative superposition technique with bulk-bias control von Dai, Ruofan, Zheng, Yunlong, Zhu, Hongwei, Kong, Weiran, Zou, Shichang

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Investigation and process optimization of SONOS cell’s drain disturb in 2-transistor structure flash arrays von Xu, Zhaozhao, Qian, Wensheng, Chen, Hualun, Xiong, Wei, Hu, Jun, Liu, Donghua, Duan, Wenting, Kong, Weiran, Na, Wei, Zou, Shichang

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Investigation and impact of LDD variations on the drain disturb in normally-on SONOS NOR flash device von Xu, Zhaozhao, Liu, Donghua, Xiong, Wei, Hu, Jun, Duan, Wenting, Chen, Hualun, Qian, Wensheng, Kong, Weiran, Zou, Shichang

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A 10-bit 2.5-MS/s SAR ADC with 60.46 dB SNDR in 0.13-μm CMOS technology von Dai, Ruofan, Zheng, Yunlong, Wang, Zi, Zhu, Hongwei, Kong, Weiran, Zou, Shichang

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Successive approximation register analog-to-digital converter and conversion method therefor von Kong, Weiran, Zhang, Bin

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SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND CONVERSION METHOD THEREFOR von ZHANG, Bin, KONG, Weiran

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Demonstration of improvement of specific on-resistance versus breakdown voltage tradeoff for low-voltage power LDMOS von Xu, Zhaozhao, Liu, Donghua, Hu, Jun, Jin, Feng, Yang, Xinjie, Duan, Wenting, Yue, Wei, Fang, Ziquan, Qian, Wensheng, Kong, Weiran, Zou, Shichang

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A 0.5-V novel complementary current-reused CMOS LNA for 2.4 GHz medical application von Dai, Ruofan, Zheng, Yunlong, He, Jun, Liu, Guojun, Kong, Weiran, Zou, Shichang

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