An Efficient Resource Shared RISC-V Multicore Architecture von ISLAM, Md Ashraful, KISE, Kenji

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High-Performance and Hardware-Efficient Odd-Even Based Merge Sorter von ELSAYED, Elsayed A., KISE, Kenji

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Emerging Processors Based on an Open Instruction Set Architecture and Domain-Specific Optimization von Kise, Kenji

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RVCar: An FPGA-Based Simple and Open-Source Mini Motor Car System with a RISC-V Soft Processor von KANAMORI, Takuto, ODAN, Takashi, HIROHATA, Kazuki, KISE, Kenji

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An Exploration of State-of-the-Art Automation Frameworks for FPGA-Based DNN Acceleration von Hamanaka, Fumio, Odan, Takashi, Kise, Kenji, Chu, Thiem Van

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A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism von KOBAYASHI, Ryohei, KISE, Kenji

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LEF: An Effective Routing Algorithm for Two-Dimensional Meshes von CHU, Thiem Van, KISE, Kenji

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RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining von MIYAZAKI, Hiromu, KANAMORI, Takuto, ISLAM, Md Ashraful, KISE, Kenji

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ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment von SATO, Shimpei, KOBAYASHI, Ryohei, KISE, Kenji

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Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA von Chu, Thiem Van, Sato, Shimpei, Kise, Kenji

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Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs von TAKAMAEDA-YAMAZAKI, Shinya, NAKATSUKA, Hiroshi, TANAKA, Yuichiro, KISE, Kenji

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A Challenge of Portable and High-Speed FPGA Accelerator von Usui, Takuma, Kobayashi, Ryohei, Kise, Kenji

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ArchHDL: A Novel Hardware RTL Design Environment in C++ von Sato, Shimpei, Kise, Kenji

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FIBER: A Generalized Framework for Auto-tuning Software von Katagiri, Takahiro, Kise, Kenji, Honda, Hiroaki, Yuba, Toshitsugu

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ABCLibScript: a directive to support specification of an auto-tuning facility for numerical software von Katagiri, Takahiro, Kise, Kenji, Honda, Hiroki, Yuba, Toshitsugu

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Longitudinal Changes in Functional Independence Measure Motor Subscores of Patients with Stroke Discharged to Home from a Convalescence Rehabilitation Ward von TAKAMATSU, Kenji, HIRAMATSU, Yuichi, FUJITA, Nobukazu, KISE, Kenji, ARAKI, Kazuko, MIYAI, Ichiro

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SimAlpha Version 1.0: Simple and Readable Alpha Processor Simulator von Kise, Kenji, Honda, Hiroki, Yuba, Toshitsugu

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SimCell: A Processor Simulator for Multi-Core Architecture Research von Sato, Shimpei, Fujieda, Naoki, Moriya, Akira, Kise, Kenji

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オープン命令セットのプロセッサとドメイン最適化技術 von 吉瀬, 謙二

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Parallel Processing of Matrix Multiplication in a CPU and GPU Heterogeneous Environment von Ohshima, Satoshi, Kise, Kenji, Katagiri, Takahiro, Yuba, Toshitsugu

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