A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory von Ki Chul Chun, Hui Zhao, Harms, Jonathan D., Tae-Hyoung Kim, Jian-Ping Wang, Kim, Chris H.

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A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches von Ki Chul Chun, Jain, Pulkit, Tae-Ho Kim, Kim, Chris H.

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A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches von Ki Chul Chun, Jain, P, Jung Hwa Lee, Kim, C H

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A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor von Ki Chul Chun, Wei Zhang, Jain, P., Kim, C. H.

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A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode von Wei Zhang, Ki Chul Chun, Kim, Chris H.

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A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications von Seung-Hwan Song, Ki Chul Chun, Kim, Chris H.

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An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process von Park, Jaewon, Lee, Jae Hoon, Park, Sang-Kil, Chun, Ki Chul, Sohn, Kyomin, Kang, Sungho

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Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMs von Sim, J.-Y., Kwon, K.-W., Chun, K.-C.

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A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor von Sim, Jae-Yoon, Yoon, Hongil, Chun, Ki-Chul, Lee, Hyun-Seok, Hong, Sang-Pyo, Lee, Kyu-Chan, Yoo, Jei-Hwan, Seo, Dong-Il, Cho, Soo-In

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P-79: Characterization of Narrow-Channel TFT Using Asymmetric Halftone Exposure von Chun, Ki-Chul, Woo, Juhyun, Jung, Deuk-soo, Park, Mungi, Kim, Hwan, Lim, Byoung-Ho, Yu, Sang-Jeon

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A write-back-free 2T1D embedded DRAM with local voltage sensing and a dual-row-access low power mode von Wei Zhang, Ki Chul Chun, Kim, C. H.

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A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies von Ki Chul Chun, Wei Zhang, Jain, Pulkit, Kim, Chris H

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Logic-compatible embedded DRAM design for memory intensive low power systems von Ki Chul Chun, Jain, P, Kim, C H

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A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme von Song, Seung-Hwan, Chun, Ki Chul, Kim, Chris H.

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A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme von Chun, Ki Chul, Kim, Yong Ki, Ryu, Yesin, Park, Jaewon, Oh, Chi Sung, Byun, Young Yong, Kim, So Young, Shin, Dong Hak, Lee, Jun Gyu, Ho, Byung-Kyu, Park, Min-Sang, Cho, Seong-Jin, Woo, Seunghan, Moon, Byoung Mo, Kil, Beomyong, Ahn, Sungoh, Lee, Jae Hoon, Kim, Soo Young, Choi, Seouk-Kyu, Jeong, Jae-Seung, Ahn, Sung-Gi, Kim, Jihye, Kong, Jun Jin, Sohn, Kyomin, Kim, Nam Sung, Lee, Jung-Bae

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A 1.8 V 128 Mb mobile DRAM with hidden-precharged triple pumping scheme and dual-path hybrid current sense amplifier von Chun, Ki-Chul, Sim, Jae-Yoon, Yoon, Hongil, Lee, Hyun-Seok, Hong, Sang-Pyo, Lee, Kyu-Chan, Yoo, Jei-Hwan, Seo, Dong-Il

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A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme von Seung-Hwan Song, Ki Chul Chun, Kim, C. H.

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Variation aware performance analysis of gain cell embedded DRAMs von Zhang, Wei, Chun, Ki Chul, Kim, Chris H.

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Memory device with multiple voltage generators von Park Chul-Sung, Chun Ki-Chul

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A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias von Chun, Ki Chul, Jain, Pulkit, Lee, Jung Hwa, Kim, Chris H.

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