Practical parallel imaging compressed sensing MRI: Summary of two years of experience in accelerating body MRI of pediatric patients von Vasanawala, S S, Murphy, M J, Alley, M T, Lai, P, Keutzer, K, Pauly, J M, Lustig, M

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System-level design: orthogonalization of concerns and platform-based design von Keutzer, K., Newton, A.R., Rabaey, J.M., Sangiovanni-Vincentelli, A.

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Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits von Orshansky, M., Milor, L., Pinhong Chen, Keutzer, K., Chenming Hu

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Impact of small process geometries on microarchitectures in systems on a chip von Sylvester, D., Keutzer, K.

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A global wiring paradigm for deep submicron design von Sylvester, D., Keutzer, K.

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Addressing the system-on-a-chip interconnect woes through communication-based design von Sgroi, M., Sheets, M., Mihal, A., Keutzer, K., Malik, S., Rabaey, J., Sangiovanni-Vencentelli, A.

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Linear programming for sizing, Vth and Vdd assignment von Chinnery, D. G., Keutzer, K.

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OCCOM-efficient computation of observability-based code coverage metrics for functional verification von Fallah, F., Devadas, S., Keutzer, K.

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NP-Click: a productive software development approach for network processors von Niraj Shah, Plishker, W., Kaushik Ravindran, Keutzer, K.

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Functional vector generation for HDL models using linear programming and Boolean satisfiability von Fallah, F., Devadas, S., Keutzer, K.

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Rethinking deep-submicron circuit design von Sylvester, D., Keutzer, K.

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Limitations and challenges of computer-aided design technology for CMOS VLSI von Bryant, R.E., Kwang-Ting Cheng, Kahng, A.B., Keutzer, K., Maly, W., Newton, R., Pileggi, L., Rabaey, J.M., Sangiovanni-Vincentelli, A.

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Functional vector generation for HDL models using linear programming and 3-satisfiability von Fallah, Farzan, Devadas, Srinivas, Keutzer, Kurt

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Closing the gap between ASIC and custom: an ASIC perspective von Chinnery, D G, Keutzer, K

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Bus encoding to prevent crosstalk delay von Victor, B., Keutzer, K.

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A quick safari through the reconfiguration jungle von Schaumont, Patrick, Verbauwhede, Ingrid, Keutzer, Kurt, Sarrafzadeh, Majid

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A general probabilistic framework for worst case timing analysis von Orshansky, Michael, Keutzer, Kurt

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From ASIC to ASIP: the next design discontinuity von Keutzer, K., Malik, S., Newton, A.R.

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Estimation of average switching activity in combinational logic circuits using symbolic simulation von Monteiro, J., Devadas, S., Ghosh, A., Keutzer, K., White, J.

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Accelerating Value-at-Risk estimation on highly parallel architectures von Dixon, M. F., Chong, J., Keutzer, K.

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