Optimal Selective Huffman Coding for Test-Data Compression von Kavousianos, X., Kalligeros, E., Nikolos, D.

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Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores von Kavousianos, X., Kalligeros, E., Nikolos, D.

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Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability von Kavousianos, X., Kalligeros, E., Nikolos, D.

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Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains von Kavousianos, X., Kalligeros, E., Nikolos, D.

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Defect aware X-filling for low-power scan testing von Balatsouka, S, Tenentes, V, Kavousianos, X, Chakrabarty, K

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A Robust and Reconfigurable Multi-mode Power Gating Architecture von Zhang, Z, Kavousianos, X, Chakrabarty, K, Tsiatouhas, Y

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Multiphase BIST: a new reseeding technique for high test-data compression von Kalligeros, E., Kavousianos, X., Nikolos, D.

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Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands von Kavousianos, X., Chakrabarty, K., Jain, A., Parekhji, R.

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Single and Variable-State-Skip LFSRs: Bridging the Gap Between Test Data Compression and Test Set Embedding for IP Cores von Tenentes, V, Kavousianos, X, Kalligeros, E

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Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets von Kavousianos, X., Tenentes, V., Chakrabarty, K., Kalligeros, E.

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A new built-in TPG method for circuits with random pattern resistant faults von Kavousianos, X., Bakalis, D., Nikolos, D., Tragoudas, S.

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Low Power Test-Compression for High Test-Quality and Low Test-Data Volume von Tenentes, Vasileios, Kavousianos, X.

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Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands von Kavousianos, X., Chakrabarty, K., Jain, A., Parekhji, R.

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Novel Single and Double Output TSC CMOS Checkers for m-out-of-n Codes von Kavousianos, X., Nikolos, D., Sidiropoulos, G.

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New efficient totally self-checking Berger code checkers von Kavousianos, X., Nikolos, D., Foukarakis, G., Gnardellis, T.

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State Skip LFSRs: Bridging the Gap between Test Data Compression and Test Set Embedding for IP Cores von Tenentes, V., Kavousianos, X., Kalligeros, E.

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Generation of compact test sets with high defect coverage von Kavousianos, X., Chakrabarty, K.

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Self-Freeze Linear Decompressors for Low Power Testing von Tenentes, V, Kavousianos, X

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Low Power Built-In Self-Test Schemes for Array and Booth Multipliers von Bakalist, D., Kavousianos, X., Vergos, H. T., Nikolos, D., Alexiou, G. Ph

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Modelling, Design, and Performance Comparison of Triple Gate Cylindrical and Partially Cylindrical FinFETs for Low-Power Applications von Rai, Sanjeev, Sahu, Jyotsna, Dattatray, Wanjul, Mishra, R. A., Tiwari, Sudarshan

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