High- $kappa$ /Metal–Gate Stack and Its MOSFET Characteristics von Chau, R, Datta, S, Doczy, M, Doyle, B, Kavalieros, J, Metz, M

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Benchmarking nanotechnology for high-performance and low-power logic transistor applications von Chau, R., Datta, S., Doczy, M., Doyle, B., Jin, B., Kavalieros, J., Majumdar, A., Metz, M., Radosavljevic, M.

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High performance fully-depleted tri-gate CMOS transistors von Doyle, B.S., Datta, S., Doczy, M., Hareland, S., Jin, B., Kavalieros, J., Linton, T., Murthy, A., Rios, R., Chau, R.

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BTI reliability of 45 nm high-K + metal-gate process technology von Pae, S., Agostinelli, M., Brazier, M., Chau, R., Dewey, G., Ghani, T., Hattendorf, M., Hicks, J., Kavalieros, J., Kuhn, K., Kuhn, M., Maiz, J., Metz, M., Mistry, K., Prasad, C., Ramey, S., Roskowski, A., Sandford, J., Thomas, C., Thomas, J., Wiegand, C., Wiedemer, J.

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Direct-current measurements of oxide and interface traps on oxidized silicon von Neugroschel, A., Chih-Tang Sah, Han, K.M., Carroll, M.S., Nishida, T., Kavalieros, J.T., Yi Lu

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Inversion MOS capacitance extraction for high-leakage dielectrics using a transmission line equivalent circuit von Barlage, D.W., O'Keeffe, J.T., Kavalieros, J.T., Nguyen, M.M., Chau, R.S.

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Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology von Chau, Robert, Brask, Justin, Datta, Suman, Dewey, Gilbert, Doczy, Mark, Doyle, Brian, Kavalieros, Jack, Jin, Ben, Metz, Matthew, Majumdar, Amlan, Radosavljevic, Marko

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Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering von Kavalieros, J., Doyle, B., Datta, S., Dewey, G., Doczy, M., Jin, B., Lionberger, D., Metz, M., Rachmady, W., Radosavljevic, M., Shah, U., Zelick, N., Chau, R.

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Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applica... von Radosavljevic, M, Dewey, G, Fastenau, J M, Kavalieros, J, Kotlyar, R, Chu-Kung, B, Liu, W K, Lubyshev, D, Metz, M, Millard, K, Mukherjee, N, Pan, L, Pillarisetty, R, Rachmady, W, Shah, U, Chau, R

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Heterogeneous integration of enhancement mode in0.7ga0.3as quantum well transistor on silicon substrate using thin (les 2 μm) composite buffer architecture for high-speed and low-v... von Hudait, M.K., Dewey, G., Datta, S., Fastenau, J.M., Kavalieros, J., Liu, W.K., Lubyshev, D., Pillarisetty, R., Rachmady, W., Radosavljevic, M., Rakshit, T., Chau, R.

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Fabrication, characterization, and physics of III-V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing von Dewey, G., Chu-Kung, B., Boardman, J., Fastenau, J. M., Kavalieros, J., Kotlyar, R., Liu, W. K., Lubyshev, D., Metz, M., Mukherjee, N., Oakey, P., Pillarisetty, R., Radosavljevic, M., Then, H. W., Chau, R.

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Advanced Si and SiGe strained channel NMOS and PMOS transistors with high-k/metal-gate stack von Datta, S., Brask, J., Dewey, G., Doczy, M., Doyle, B., Ben Jin, Kavalieros, J., Metz, M., Majumdar, A., Radosavljevic, M., Chau, R.

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High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III-V CMOS architecture von Pillarisetty, R, Chu-Kung, B, Corcoran, S, Dewey, G, Kavalieros, J, Kennel, H, Kotlyar, R, Le, V, Lionberger, D, Metz, M, Mukherjee, N, Nah, J, Rachmady, W, Radosavljevic, M, Shah, U, Taft, S, Then, H, Zelick, N, Chau, R

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Profiling interface traps in MOS transistors by the DC current-voltage method von Chih-Tang Sah, Neugroschel, A., Han, K.M., Kavalieros, J.T.

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Silicon nano-transistors for logic applications von Chau, Robert, Boyanov, Boyan, Doyle, Brian, Doczy, Mark, Datta, Suman, Hareland, Scott, Jin, Ben, Kavalieros, Jack, Metz, Matthew

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MOVPE III-V material growth on silicon substrates and its comparison to MBE for future high performance and low power logic applications von Mukherjee, N., Boardman, J., Chu-Kung, B., Dewey, G., Eisenbach, A., Fastenau, J., Kavalieros, J., Liu, W. K., Lubyshev, D., Metz, M., Millard, K., Radosavljevic, M., Stewart, T., Then, H. W., Tolchinsky, P., Chau, R.

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High-/spl kappa//metal-gate stack and its MOSFET characteristics von Chau, R., Datta, S., Doczy, M., Doyle, B., Kavalieros, J., Metz, M.

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High-[kappa]/metal-gate stack and its MOSFET characteristics von Chau, R, Datta, S, Doczy, M, Doyle, B, Kavalieros, J, Metz, M

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Silicon nano-transistors and breaking the 10 nm physical gate length barrier von Chau, R., Doyle, B., Doczy, M., Datta, S., Hareland, S., Jin, B., Kavalieros, J., Metz, M.

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Dielectric breakdown in a 45 nm high-k/metal gate process technology von Prasad, C., Agostinelli, M., Auth, C., Brazier, M., Chau, R., Dewey, G., Ghani, T., Hattendorf, M., Hicks, J., Jopling, J., Kavalieros, J., Kotlyar, R., Kuhn, M., Kuhn, K., Maiz, J., McIntyre, B., Metz, M., Mistry, K., Pae, S., Rachmady, W., Ramey, S., Roskowski, A., Sandford, J., Thomas, C., Wiegand, C., Wiedemer, J.

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