Minimum Unit Capacitance Calculation for Capacitor Arrays in Binary-Weighted and Split DACs von Karmokar, Nibedita, Harjani, Ramesh, Sapatnekar, Sachin S.

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Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs von Karmokar, Nibedita, Sharma, Arvind K., Poojary, Jitesh, Madhusudan, Meghna, Harjani, Ramesh, Sapatnekar, Sachin S.

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Machine Learning for Analog Layout von Burns, Steven M., Chen, Hao, Dhar, Tonmoy, Harjani, Ramesh, Hu, Jiang, Karmokar, Nibedita, Kunal, Kishor, Li, Yaguang, Lin, Yishuang, Liu, Mingjie, Madhusudan, Meghna, Mukherjee, Parijat, Pan, David Z., Poojary, Jitesh, Ramprasath, S., Sapatnekar, Sachin S., Sharma, Arvind K., Xu, Wenbin, Yaldiz, Soner, Zhu, Keren

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