Design impacts of delay invariant high-speed clock delayed dual keeper domino circuit von Angeline, A. Anita, Kanchana Bhaaskaran, V.S

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Secured Communication System Architecture Using Light Weight Algorithms von Prathiba, A., Kanchana Bhaaskaran, V.S.

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Performance Analysis of 2N-N-2P Adiabatic Logic Circuits for Low Power Applications using FinFET von Bhuvana, B.P., Kanchana Bhaaskaran, V.S.

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Ultra Low Power, High Performance Negative Edge Triggered ECRL Energy Recovery Sequential Elements with Power Clock Gating von Jennifer Judy, D., Kanchana Bhaaskaran, V.S.

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Design of FinFET-based Energy Efficient Pass-Transistor Adiabatic Logic for ultra-low power applications von Bhuvana, B.P., Kanchana Bhaaskaran, V.S.

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Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems von Prathiba, A., Kanchana Bhaaskaran, V.S.

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Design and analysis of IPAL for ultra low power CRC architecture for applications in IoT based systems von Bhuvana, B.P., Kanchana Bhaaskaran, V.S.

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Frontiers in Electronic Technologies: Trends and Challenges von Prabaharan, S. R. S, Thalmann, Nadia Magnenat, Kanchana Bhaaskaran, V. S

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Energy Recovery Logic using FinFET von Shatakshi Panda, Soumya, Judy, D. Jennifer, Kanchana Bhaaskaran, V.S.

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High speed wide fan-in designs using clock controlled dual keeper domino logic circuits von Angeline, A. Anita, Bhaaskaran, V.S. Kanchana

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A New Improved MCML Logic for DPA Resistant Circuits von A.K, Tripathy, A, Prathiba, V.S, Kanchana Bhaaskaran

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Matrix Code Based Multiple Error Correction Technique for N-Bit Memory Data von Sunita, M S, Bhaaskaran, V S Kanchana

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Semi-custom design of adiabatic adder circuits von Kanchana Bhaaskaran, V.S., Salivahanan, S., Emmanuel, D.S.

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Single phase clocked quasi static adiabatic tree adder von Sasipriya, P., Kanchana, B. V. S.

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