Arbiter PUF - A Review of Design, Composition, and Security Aspects von Hemavathy, S, Kanchana Bhaaskaran, V S

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High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits von Anita Angeline, A., Kanchana Bhaaskaran, V. S.

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Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems von Prathiba, A., Kanchana Bhaaskaran, V.S.

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Frontiers in Electronic Technologies: Trends and Challenges von Prabaharan, S. R. S, Thalmann, Nadia Magnenat, Kanchana Bhaaskaran, V. S

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Design of energy efficient carry lookahead adder using novel CSIPGL adiabatic logic circuit von Bhalerao, Abhishek L, Mane, Aishwarya, Pensenwar, Kartik, Bhuvana, B P, Anita Angeline, A, Kanchana Bhaaskaran, V S

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Lightweight S-Box Architecture for Secure Internet of Things von Prathiba, A., Bhaaskaran, V.

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Adaptive PUF design to authenticate and evaluate heterogeneous IPs in edge computing von Hemavathy, S., Kokila, J., Kanchana Bhaaskaran, V. S.

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Design of FinFET-based Energy Efficient Pass-Transistor Adiabatic Logic for ultra-low power applications von Bhuvana, B.P., Kanchana Bhaaskaran, V.S.

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Design impacts of delay invariant high-speed clock delayed dual keeper domino circuit von Angeline, A. Anita, Kanchana Bhaaskaran, V.S

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Design and analysis of IPAL for ultra low power CRC architecture for applications in IoT based systems von Bhuvana, B.P., Kanchana Bhaaskaran, V.S.

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Domino Logic Keeper Circuit Design Techniques: A Review von Angeline, A. Anita, Bhaaskaran, V. S. Kanchana

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High Speed and Low Power Implementation of AES for Wireless Sensor Networks von Thangarajan, Sreenath, Bhaaskaran, V S Kanchana

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Low Power Memory System Design Using Power Gated SRAM Cell von Pal, Srijani, Salimath, Divya S, Chandran, Banusha, Anita Angeline, A, Kanchana Bhaaskaran, V S

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High Performance Wallace Tree Multiplier Using Majority Gate Based Adders von Mummudi Murasu, M, Sujith, Sanjana, Anita Angeline, A, Sasi Priya, P., Kanchana Bhaaskaran, V S

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Adiabatic SRAM Cell and Array von Manna, Ayon, Kanchana Bhaaskaran, V. S.

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Performance Analysis of 2N-N-2P Adiabatic Logic Circuits for Low Power Applications using FinFET von Bhuvana, B.P., Kanchana Bhaaskaran, V.S.

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Energy Recovery Logic using FinFET von Shatakshi Panda, Soumya, Judy, D. Jennifer, Kanchana Bhaaskaran, V.S.

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Design of a 16 Bit RISC Processor von Vishnuvardhan Rao, K., Anita Angeline, A., Kanchana Bhaaskaran, V. S.

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LOW POWER 64-BIT CARRY SELECT ADDER USING MODIFIED EXNOR BLOCK von Srinivasa, Raghavan B, Bhuvana, B P, Kanchana, Bhaaskaran V S

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Schmitt Trigger Designs Using Domino Logic Style von Singh, Nikhil, Shekhar, Siddharth, Angeline, Anita, Bhaaskaran V. S, Kanchana

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