Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield von Sakui, Koji, Li, Yisuo, Kakumu, Masakazu, Kanazawa, Kenichi, Kunishima, Iwao, Iwata, Yoshihisa, Harada, Nozomu

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FERROELECTRIC PROPERTIES OF Pb(Zr, Ti)O3 CAPACITOR WITH THIN SrRuO3 FILMS WITHIN BOTH ELECTRODES von Morimoto, T, Hidaka, O, Yamakawa, K, Arisumi, O, Kanaya, H, Iwamoto, T

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A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes von Shiga, H., Takashima, D., Shiratake, S., Hoya, K., Miyakawa, T., Ogiwara, R., Fukuda, R., Takizawa, R., Hatsuda, K., Matsuoka, F., Nagadomi, Y., Hashimoto, D., Nishimura, H., Hioka, T., Doumae, S., Shimizu, S., Kawano, M., Taguchi, T., Watanabe, Y., Fujii, S., Ozaki, T., Kanaya, H., Kumura, Y., Shimojo, Y., Yamada, Y., Minami, Y., Shuto, S., Yamakawa, K., Yamazaki, S., Kunishima, I., Hamamoto, T., Nitayama, A., Furuyama, T.

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A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode von Hoya, Katsuhiko, Takashima, D, Shiratake, S, Ogiwara, R, Miyakawa, T, Shiga, H, Doumae, S M, Ohtsuki, S, Kumura, Y, Shuto, S, Ozaki, T, Yamakawa, K, Kunishima, I, Nitayama, A, Fujii, S

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Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI von Morimoto, T., Ohguro, T., Momose, S., Iinuma, T., Kunishima, I., Suguro, K., Katakabe, I., Nakajima, H., Tsuchiaki, M., Ono, M., Katsumata, Y., Iwai, H.

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A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs von Takashima, D., Shiga, H., Hashimoto, D., Miyakawa, T., Shiratake, S., Hoya, K., Ogiwara, R., Takizawa, R., Doumae, S., Fukuda, R., Watanabe, Y., Fujii, S., Ozaki, T., Kanaya, H., Shuto, S., Yamakawa, K., Kunishima, I., Hamamoto, T., Nitayama, A.

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High-density chain ferroelectric random access memory (chain FRAM) von Takashima, D., Kunishima, I.

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Homogeneous heteroepitaxial NiSi2 formation on (100)Si von KUNISHIMA, I, SUGURO, K, AOYAMA, T, MATSUNAGA, J

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Anomalous junction leakage behavior of Ti self aligned silicide contacts on ultra-shallow junctions von SAKATA, A, TOMITA, M, KOIKE, M, KOYAMA, M, KUNISHIMA, I

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LAMINATE STRUCTURE AND METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR DEVICE von KAMATA Yoshiki, TOMINAGA Junji, KUNISHIMA Iwao, MIYATA Noriyuki

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A 76-mm(2) 8-Mb chain ferroelectric memory von Takashima, D, Takeuchi, Y, Miyakawa, T, Itoh, Y, Ogiwara, R, Kamoshida, M, Hoya, K, Doumae, S M, Ozaki, T, Kanaya, H, Yamakawa, K, Kunishima, I, Oowaki, Y

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A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes von Shiga, H., Takashima, D., Shiratake, S., Hoya, K., Miyakawa, T., Ogiwara, R., Fukuda, R., Takizawa, R., Hatsuda, K., Matsuoka, F., Nagadomi, Y., Hashimoto, D., Nishimura, H., Hioka, T., Doumae, S., Shimizu, S., Kawano, M., Taguchi, T., Watanabe, Y., Fujii, S., Ozaki, T., Kanaya, H., Kumura, Y., Shimojo, Y., Yamada, Y., Minami, Y., Shuto, S., Yamakawa, K., Yamazaki, S., Kunishima, I., Hamamoto, T., Nitayama, A., Furuyama, T.

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STACKED STRUCTURE AND METHOD OF MANUFACTURING SAME, AND SEMICONDUCTOR DEVICE von Tominaga, Junji, Kunishima, Iwao, Kamata, Yoshiki, Miyata, Noriyuki

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A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM von Takashima, D., Shiga, H., Hashimoto, D., Miyakawa, T., Shiratake, S., Hoya, K., Ogiwara, R., Takizawa, R., Doumae, S., Fukuda, R., Watanabe, Y., Fujii, S., Ozaki, T., Kanaya, H., Shuto, S., Yamakawa, K., Kunishima, I., Hamamoto, T., Nitayama, A.

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LAMINATE STRUCTURE AND METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR DEVICE von KAMATA Yoshiki, TOMINAGA Junji, KUNISHIMA Iwao, MIYATA Noriyuki

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High-density and high-speed 128Mb chain FeRAM™ with SDRAM-compatible DDR2 interface von Shimojo, Y., Konno, A., Nishimura, J., Okada, T., Yamada, Y., Kitazaki, S., Furuhashi, H., Yamazaki, S., Yahashi, K., Tomioka, K., Minami, Y., Kanaya, H., Shuto, S., Yamakawa, K., Ozaki, T., Shiga, H., Miyakawa, T., Shiratake, S., Takashima, D., Kunishima, I., Hamamoto, T., Nitayama, A.

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A 32-Mb chain FeRAM with segment/stitch array architecture von Shiratake, S., Miyakawa, T., Takeuchi, Y., Ogiwara, R., Kamoshida, M., Hoya, K., Oikawa, K., Ozaki, T., Kunishima, I., Yamakawa, K., Sugimoto, S., Takashima, D., Joachim, H.-O., Rehm, N., Wohlfahrt, J., Nagel, N., Beitel, G., Jacob, M., Roehr, T.

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A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive von Takashima, D., Shuto, S., Kunishima, I., Takenaka, H., Oowaki, Y., Tanaka, S.

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Nonvolatile memory device and method of manufacturing the same von Kunishima, Iwao, Kamata, Yoshiki, Morota, Misako, Asao, Yoshiaki, Nomura, Yukihiro

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NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME von MOROTA, Misako, NOMURA, Yukihiro, ASAO, Yoshiaki, KAMATA, Yoshiki, KUNISHIMA, Iwao

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