Fast statistical timing analysis by probabilistic event propagation von Liou, Jing-Jia, Cheng, Kwang-Ting, Kundu, Sandip, Krstic, Angela

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False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation von Jing-Jia Liou, Krstic, A., Wang, L.-C., Kwang-Ting Cheng

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Vector generation for maximum instantaneous current through supply lines for CMOS circuits von Krstic, Angela, Cheng, Kwang-Ting

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Current directions in automatic test-pattern generation von Kwang-Ting Cheng, Krstic, A.

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Estimation for maximum instantaneous current through supply lines for CMOS circuits von Yi-Min Jiang, Krstic, A., Kwang-Ting Cheng

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Delay defect diagnosis based upon statistical timing models - the first step [logic testing] von Krstic, A., Wang, L.-C., Kwang-Ting Cheng, Jing-Jia Liou, Abadir, M.S.

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Pattern generation for delay testing and dynamic timing analysis considering power-supply noise effects von Krstic, A., Yi-Min Jiang, Kwang-Ting Cheng

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Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices von Jing-Jia Liou, Krstic, A., Yi-Ming Jiang, Kwang-Ting Cheng

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Test program synthesis for path delay faults in microprocessor cores von Wei-Cheng Lai, Krstic, A., Kwang-Ting Cheng

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Generation of high quality tests for robustly untestable path delay faults von Kwang-Ting Cheng, Krstic, A., Hsi-Chuan Chen

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Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability von Krstic, Angela, Cheng, Kwang-ting

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Embedded software-based self-testing for SoC design von Kirstic, A., Lai, W.-C., Chen, L., Cheng, K.-T., Dey, S.

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Primitive delay faults: identification, testing, and design for testability von Krstic, A., Kwang-Ting Cheng, Chakradhar, S.T.

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Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step von Krstic, Angela, Wang, Li-C., Cheng, Kwang-Ting, Liou, Jing-Jia, Abadir, Magdy S.

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Delay testing considering power supply noise effects von Krstic, A., Yi-Min Jiang, Kwang-Ting Cheng

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Post-layout Logic Restructuring For Performance Optimization von Yi-Min Jiang, Krstic, A., Kwang-Ting Cheng, Marek-Sadowska, M.

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Path selection and pattern generation for dynamic timing analysis considering power supply noise effects von Jing-Jia Liou, Krstic, A., Yi-Min Jiang, Kwang-Ting Cheng

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False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation von Liou, Jing-Jia, Krstic, Angela, Wang, Li-C., Cheng, Kwang-Ting

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Delay testing considering crosstalk-induced effects von Krstic, A., Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng

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Embedded software-based self-test for programmable core-based designs von Krstic, A., Wei-Cheng Lai, Kwang-Ting Cheng, Chen, L., Dey, S.

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