A Simultaneous Bidirectional Single-Ended Coaxial Link With 24-Gb/s Forward and 312.5-Mb/s Back Channels von Manian, Abishek, Rane, Amit, Koh, Yongseon, Nat, Harsheen Kaur, Lu, Michael

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DUTY-CYCLE CALIBRATION BASED ON DIFFERENTIAL CLOCK SENSING von KOH, Yongseon, RIBEIRO, Roland, GIUROIU, Horia

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A 33 mW 12.5 Gbps BiCMOS transmitter for high speed backplane applications von Abugharbieh, Khaldoon, Koh, Yongseon, Krishnan, Shoba, Mohan, Jitendra

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Differential analog signal processing stage with reduced even order harmonic distortion von LEE BUMHA, KOH YONGSEON

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DIFFERENTIAL ANALOG SIGNAL PROCESSING STAGE WITH REDUCED EVEN ORDER HARMONIC DISTORTION von LEE BUMHA, KOH YONGSEON

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A 33mW 12.5Gbps BiCMOS transmitter for high speed backplane applications von Abugharbieh, Khaldoon, Koh, Yongseon, Krishnan, Shoba, Mohan, Jitendra

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Method of forming a semiconductor die with reduced RF attenuation von Babcock, Jeffrey A, Koh, Yongseon

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Method of forming a semiconductor die with reduced RF attenuation von BABCOCK JEFFREY A, KOH YONGSEON

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Method for generating non-overlapping N-phases of divide-by-N clocks with precise 1/N duty ratio using a shift register von KOH YONGSEON, MOHAN JITENDRA

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Method for generating non-overlapping N-phases of divide-by-N clocks with precise 1/N duty ratio using a shift register von Koh, Yongseon, Mohan, Jitendra

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Complementary source coupled logic von KOH YONGSEON

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Semiconductor die with reduced RF attenuation von Babcock, Jeffrey A, Koh, Yongseon

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Semiconductor die with reduced RF attenuation von BABCOCK JEFFREY A, KOH YONGSEON

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Built-in test circuit for testing AC transfer characteristic of high-speed analog circuit von MATINPOUR BABAK, KOH YONGSEON, CEEKALA VIJAYA

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Built-in test circuit for testing AC transfer characteristic of high-speed analog circuit von Koh, Yongseon, Matinpour, Babak, Ceekala, Vijaya

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Fault state detection mechanism for a ring-counter-based frequency divider-by-N that generates non-overlapping N-phases of divide-by-N clocks with 1/N duty ratio von Koh, Yongseon, Mohan, Jitendra

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Fault state detection mechanism for a ring-counter-based frequency divider-by-N that generates non-overlapping N-phases of divide-by-N clocks with 1/N duty ratio von KOH YONGSEON, MOHAN JITENDRA

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System and method for providing adaptively equalized data signal with alternately adjusted data signal boost and sliced data signal amplitude von Rane, Amit, Nodenot, Nicolas, Koh, Yongseon, Lewicki, Laurence, Buchanan, Benjamin

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System and method for providing adaptively equalized data signal with alternately adjusted data signal boost and sliced data signal amplitude von LEWICKI LAURENCE, BUCHANAN BENJAMIN, RANE AMIT, KOH YONGSEON, NODENOT NICOLAS

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System and method for providing a constant swing high-gain complementary differential limiting amplifier von Ziazadeh, Ramsin M, Koh, Yongseon

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