The 2018 GaN power electronics roadmap von Amano, H, Baines, Y, Beam, E, Borga, Matteo, Bouchet, T, Chalker, Paul R, Charles, M, Chen, Kevin J, Chowdhury, Nadim, Chu, Rongming, De Santi, Carlo, De Souza, Maria Merlyne, Decoutere, Stefaan, Di Cioccio, L, Eckardt, Bernd, Egawa, Takashi, Fay, P, Freedsman, Joseph J, Guido, L, Häberlen, Oliver, Haynes, Geoff, Heckel, Thomas, Hemakumara, Dilini, Houston, Peter, Hu, Jie, Hua, Mengyuan, Huang, Qingyun, Huang, Alex, Jiang, Sheng, Kawai, H, Kinzer, Dan, Kuball, Martin, Kumar, Ashwani, Lee, Kean Boon, Li, Xu, Marcon, Denis, März, Martin, McCarthy, R, Meneghesso, Gaudenzio, Meneghini, Matteo, Morvan, E, Nakajima, A, Narayanan, E M S, Oliver, Stephen, Palacios, Tomás, Piedra, Daniel, Plissonnier, M, Reddy, R, Sun, Min, Thayne, Iain, Torres, A, Trivellin, Nicola, Unni, V, Uren, Michael J, Van Hove, Marleen, Wallis, David J, Wang, J, Xie, J, Yagi, S, Yang, Shu, Youtsey, C, Yu, Ruiyang, Zanoni, Enrico, Zeltner, Stefan, Zhang, Yuhao

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Chairman's message

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Trends of Power Electronic Packaging and Modeling von Yong Liu, Irving, S., Luk, T., Kinzer, D.

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Power semiconductor and IC technologies in audiovisual applications von Kinzer, D.

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Wide bandgap boost for renewables von Kinzer, Dan

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SiC BJT minimizes losses in alternative energy applications von Niemela, Van, Ravishunkar, Arvind, Kinzer, Dan

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Challenges of power electronic packaging and modeling von Yong Liu, Kinzer, D

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Advanced power semiconductors and ICs for DC/DC converter applications von Kinzer, Dan

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Monolithic HV GaN Power ICs: Performance and application von Kinzer, Dan, Oliver, Stephen

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Integrated design environment for DC/DC converter FET optimization von Sodhi, R., Brown, S., Kinzer, D.

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Modeling for critical design and performance of wafer level chip scale package von Yong Liu, Qiuxiao Qian, Ring, Matt, Jihwan Kim, Kinzer, D.

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Wafer level stack die package von Kinzer, Dan, Liu, Yong, Martin, Stephen

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Wafer level stack die package von KINZER DAN, MARTIN STEPHEN, LIU YONG

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WAFER LEVEL STACK DIE PACKAGE von KINZER DAN, MARTIN STEPHEN, LIU YONG

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Wafer level stack die package von Kinzer, Dan, Liu, Yong, Martin, Stephen

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Wafer level stack die package von KINZER DAN, MARTIN STEPHEN, LIU YONG

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WAFER LEVEL STACK DIE PACKAGE von KINZER DAN, MARTIN STEPHEN, LIU YONG

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Wafer level stack die package von LIU, YONG, MARTIN, STEPHEN, KINZER, DAN

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3D channel architecture for semiconductor devices von HO IHSIU, KINZER DAN, CHALLA ASHOK, JO SEOKJIN, KIM SUKU, SAPP STEVEN, CALAFUT DAN, LARSEN MARK

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Modeling for defects impact on electrical performance of power packages von Yumin Liu, Chung-Lin Wu, Yong Liu, Kinzer, Dan, Jeon, O S

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