Fabrication of 5-20 nm thick β -W films von Narasimham, Avyaya J., Medikonda, Manasa, Matsubayashi, Akitomo, Khare, Prasanna, Chong, Hyuncher, Matyi, Richard J., Diebold, Alain, LaBella, Vincent P.

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Pulsed-N2 assisted growth of 5-20 nm thick β -W films von Narasimham, Avyaya J., Green, Avery, Matyi, Richard J., Khare, Prasanna, Vo, Tuan, Diebold, Alain, LaBella, Vincent P.

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Ultra-low resistivity in-situ phosphorus doped Si and SiC epitaxy for source/drain formation in advanced 20 nm n-type field effect transistor devices von LOUBET, Nicolas, ADAM, Thomas, DORIS, Bruce, SAMPSON, Ron, RAYMOND, Mark, QING LIU, KANGGUO CHENG, SREENIVASAN, Raghavasimhan, REZNICEK, Alexander, KHARE, Prasanna, KLEEMEIER, Walter, PARUCHURI, Vamsi

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Pulsed-N{sub 2} assisted growth of 5-20 nm thick β-W films von Narasimham, Avyaya J., Green, Avery, Matyi, Richard J., Khare, Prasanna, Vo, Tuan, Diebold, Alain, LaBella, Vincent P.

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Ultra-low resistivity in-situ phosphorus doped Si and SiC epitaxy for source/drain formation in advanced 20nm n-type field effect transistor devices von Loubet, Nicolas, Adam, Thomas, Raymond, Mark, Liu, Qing, Cheng, Kangguo, Sreenivasan, Raghavasimhan, Reznicek, Alexander, Khare, Prasanna, Kleemeier, Walter, Paruchuri, Vamsi, Doris, Bruce, Sampson, Ron

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METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE von KHARE, Prasanna, LOUBET, Nicolas

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Optimization of SiC:P Raised Source Drain Epitaxy for Planar 20nm Fully Depleted SOI MOSFET Structures von Loubet, Nicolas, Nagumo, Toshiharu, Adam, Thomas, Liu, Qing, Raymond, Mark, Cheng, Kangguo, Khakifirooz, Ali, Zhu, Zhengmao, Khare, Prasanna, Paruchuri, Vamsi K., Doris, Bruce, Sampson, Ron

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METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES von Loubet, Nicolas, Khare, Prasanna, Liu, Qing

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MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS von LIU, Qing, KHARE, Prasanna, LOUBET, Nicolas

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Method to co-integrate SiGe and Si channels for finFET devices von Loubet, Nicolas, Khare, Prasanna, Liu, Qing

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Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods von Loubet, Nicolas, Khare, Prasanna, Liu, Qing

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Fully substrate-isolated FinFET transistor von Loubet, Nicolas, Khare, Prasanna

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Electronic Device Including Shallow Trench Isolation (STI) Regions with Bottom Nitride Linear and Upper Oxide Linear and Related Methods von Loubet, Nicolas, Khare, Prasanna, Liu, Qing

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METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE von KHARE, Prasanna, LOUBET, Nicolas

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MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS von LIU, Qing, KHARE, Prasanna, LOUBET, Nicolas

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Method of making a semiconductor device using a dummy gate von Loubet, Nicolas, Khare, Prasanna

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FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR von KHARE, Prasanna, LOUBET, Nicolas

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Multi-fin FINFET device including epitaxial growth barrier on outside surfaces of outermost fins and related methods von Loubet, Nicolas, Khare, Prasanna, Liu, Qing

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Method of making a semiconductor device using a dummy gate von Loubet Nicolas, Khare Prasanna

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Fully substrate-isolated FinFET transistor von Loubet Nicolas, Khare Prasanna

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