The last silicon transistor: Nanosheet devices could be the final evolutionary step for Moore's Law von Ye, Peide, Ernst, Thomas, Khare, Mukesh V.

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CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials von JAMMY RAJARAO, SUNG CHUN-YUNG, WISE RICHARD, ZHANG YING, IEONG MEIKEI, YAN HONGWEN, CHEN TZEIANG, KHARE MUKESH V

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Mechanism and process dependence of negative bias temperature instability (NBTI) for pMOSFETs with ultrathin gate dielectrics von Liu, C.H., Lee, M.T., Chih-Yung Lin, Chen, J., Schruefer, K., Brighten, J., Rovedo, N., Hook, T.B., Khare, M.V., Shih-Fen Huang, Wann, C., Tze-Chiang Chen, Ning, T.H.

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Protecting exposed metal gate structures from etching processes in integrated circuit manufacturing von Khare, Mukesh V, Mo, Renee T, Ramachandran, Ravikumar, Wise, Richard S, Yan, Hongwen

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Protecting exposed metal gate structures from etching processes in integrated circuit manufacturing von MO RENEE T, RAMACHANDRAN RAVIKUMAR, YAN HONGWEN, WISE RICHARD S, KHARE MUKESH V

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High-K metal gate CMOS von MO RENEE T, CHUDZIK MICHAEL P, NARAYANAN VIJAY, BU HUIMING, HENSON WILLIAM K, KHARE MUKESH V

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High-K metal gate CMOS von Mo, Renee T, Bu, Huiming, Chudzik, Michael P, Henson, William K, Khare, Mukesh V, Narayanan, Vijay

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CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND GATE MATERIALS von JAMMY RAJARAO, SUNG CHUN-YUNG, WISE RICHARD, ZHANG YING, IEONG MEIKEI, YAN HONGWEN, CHEN TZEIANG, KHARE MUKESH V

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CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials von Chen, Tze-Chiang, Ieong, Meikei, Jammy, Rajarao, Khare, Mukesh V, Sung, Chun-yung, Wise, Richard, Yan, Hongwen, Zhang, Ying

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CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials von JAMMY RAJARAO, SUNG CHUN-YUNG, WISE RICHARD, ZHANG YING, IEONG MEIKEI, YAN HONGWEN, CHEN TZEIANG, KHARE MUKESH V

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HIGH-K METAL GATE CMOS von MO RENEE T, CHUDZIK MICHAEL P, NARAYANAN VIJAY, BU HUIMING, HENSON WILLIAM K, KHARE MUKESH V

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High-K metal gate CMOS von MO RENEE T, CHUDZIK MICHAEL P, NARAYANAN VIJAY, BU HUIMING, HENSON WILLIAM K, KHARE MUKESH V

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High-K Metal Gate CMOS von MO RENEE T, CHUDZIK MICHAEL P, NARAYANAN VIJAY, BU HUIMING, HENSON WILLIAM K, KHARE MUKESH V

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CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND GATE MATERIALS von JAMMY RAJARAO, SUNG CHUN-YUNG, WISE RICHARD, ZHANG YING, IEONG MEIKEI, YAN HONGWEN, CHEN TZEIANG, KHARE MUKESH V

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CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials von JAMMY RAJARAO, SUNG CHUN-YUNG, WISE RICHARD, ZHANG YING, IEONG MEIKEI, YAN HONGWEN, CHEN TZEIANG, KHARE MUKESH V

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CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials von Chen, Tze-Chiang, Ieong, Meikei, Jammy, Rajarao, Khare, Mukesh V, Sung, Chun-yung, Wise, Richard, Yan, Hongwen, Zhang, Ying

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CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials von JAMMY RAJARAO, SUNG CHUN-YUNG, WISE RICHARD, ZHANG YING, IEONG MEIKEI, YAN HONGWEN, CHEN TZEIANG, KHARE MUKESH V

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Nitrided ultra thin gate dielectrics von Khare, Mukesh V, D'Emic, Christopher P, Hwang, Thomas T, Jamison, Paul C, Quinlivan, James J, Ward, Beth A

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Nitrided ultra thin gate dielectrics von QUINLIVAN JAMES J, HWANG THOMAS T, WARD BETH A, D'EMIC CHRISTOPHER P, JAMISON PAUL C, KHARE MUKESH V

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Method for improved plasma nitridation of ultra thin gate dielectrics von KHARE, MUKESH V, D'EMIC, CHRISTOPHER P, QUINLIVAN, J. J., HWANG, THOMAS T, JAMISON, PAUL C

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