Methodology for Determination of Process Induced BTI Variability in MG/HK CMOS Technologies Using a Novel Matrix Test Structure von Kerber, Andreas

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Assessment of sense measurement duration on BTI degradation in MG/HK CMOS technologies using a novel stacked transistor test structure von Kerber, Andreas

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Determination of DC equivalent hot carrier stress times in scaled CMOS devices using novel AC stress methodology von Kerber, Andreas, Nigam, Tanya

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(Invited) The Past, Present and Future of High-k/Metal Gates von Choi, Kisik, Ando, Takashi, Cartier, Eduard A., Kerber, Andreas, Paruchuri, Vamsi, Iacoponi, John, Narayanan, Vijay

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Impact of Stress Mode on Stochastic BTI in Scaled MG/HK CMOS Devices von Kerber, Andreas, Srinivasan, Purushothaman

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Application of VRS Methodology for the Statistical Assessment of BTI in MG/HK CMOS Devices von Kerber, Andreas, Cartier, Eduard

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Fast Wafer-Level Stress-and-Sense Methodology for Characterization of Ring-Oscillator Degradation in Advanced CMOS Technologies von Kerber, Andreas, Xinggong Wan, Yang Liu, Nigam, Tanya

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Characterization of Fast Relaxation During BTI Stress in Conventional and Advanced CMOS Devices With HfO2/TiN Gate Stacks von KERBER, Andreas, MAITRA, Kingsuk, MAJUMDAR, Amlan, HARGROVE, Mike, CARTIER, Eduard Albert

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Voltage Ramp Stress for Bias Temperature Instability Testing of Metal-Gate/High- k Stacks von Kerber, A., Krishnan, S.A., Cartier, E.A.

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Special Issue on Reliability von Mahapatra, Souvik, Chen, Kevin J., Kaczer, Ben, Pancheri, Lucio, Rosenbaum, Elyse, Mouli, Chandra, Wong, Hei, Kerber, Andreas, Monzio Compagnoni, Christian, Koval, Randy, Meneghesso, Gaudenzio, Sheridan, David, Ramey, Stephen, Wang, Runsheng, Stathis, Jim

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Stress-induced leakage current and defect generation in nFETs with HfO2/TiN gate stacks during positive-bias temperature stress von Cartier, E., Kerber, A.

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A Fast Four-Point Sense Methodology for Extraction of Circuit-Relevant Degradation Parameters von Kerber, A, Cartier, E

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High speed Bias Temperature Instability measurements on 20nm RMG HKMG MOSFETs von Chandra, Nishant, Chandrashekhar, Sandhya, Francis, Rick, Kerber, Andreas, Srinivasan, Purushothaman, Nigam, Tanya

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High speed Bias Temperature Instability measurements on 20 nm RMG HKMG MOSFETs von CHANDRA, Nishant, CHANDRASHEKHAR, Sandhya, FRANCIS, Rick, KERBER, Andreas, SRINIVASAN, Purushothaman, NIGAM, Tanya

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On the thermal stability of atomic layer deposited TiN as gate electrode in MOS devices von Westlinder, J., Schram, T., Pantisano, L., Cartier, E., Kerber, A., Lujan, G.S., Olsson, J., Groeseneken, G.

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Impact of failure criteria on the reliability prediction of CMOS devices with ultrathin gate oxides based on voltage ramp stress von Kerber, A., Pompl, T., Rohner, M., Mosig, K., Kerber, M.

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IMPROVED DIAGNOSTIC RING OSCILLATOR CIRCUIT FOR DC AND TRANSIENT CHARACTERIZATION von KERBER, Andreas, KLIZA, Phillip

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DIAGNOSTIC RING OSCILLATOR CIRCUIT FOR DC AND TRANSIENT CHARACTERIZATION von KERBER, Andreas, KLIZA, Phillip

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A Study of Relaxation Current in High- $kappa$ Dielectric Stacks von Xu, Zhen, Pantisano, L, Kerber, A, Degraeve, R, Cartier, E, De Gendt, S, Heyns, M, Groeseneken, G

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From wafer-level gate-oxide reliability towards ESD failures in advanced CMOS technologies von Kerber, A., Rohner, M., Wallace, C., O'Riain, L., Kerber, M.

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