Scaling to the end of silicon with EDGE architectures von Burger, D., Keckler, S.W., McKinley, K.S., Dahlin, M., John, L.K., Lin, C., Moore, C.R., Burrill, J., McDonald, R.G., Yoder, W.

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Measuring Experimental Error in Microprocessor Simulation von Desikan, Rajagopalan, Burger, Doug, Keckler, Stephen W.

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GPUs and the Future of Parallel Computing von Keckler, S. W., Dally, W. J., Khailany, B., Garland, M., Glasco, D.

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Nonuniform cache architectures for wire-delay dominated on-chip caches von Changkyu Kim, Burger, D., Keckler, S.W.

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Research Challenges for On-Chip Interconnection Networks von Owens, J.D., Dally, W.J., Ho, R., Jayasimha, D.N., Keckler, S.W., Li-Shiuan Peh

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Static energy reduction techniques for microprocessor caches von Hanson, H., Hrishikesh, M.S., Agarwal, V., Keckler, S.W., Burger, D.

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Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees von Grot, Boris, Hestness, Joel, Keckler, Stephen W., Mutlu, Onur

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Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor von Gebhart, M., Keckler, S. W., Khailany, B., Krashinsky, R., Dally, W. J.

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On-Chip Interconnection Networks of the TRIPS Chip von Gratz, P., Changkyu Kim, Sankaralingam, K., Hanson, H., Shivakumar, P., Keckler, S.W., Burger, D.

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Exploiting ILP, TLP, and DLP with the polymorphous trips architecture von Sankaralingam, K., Nagarajan, R., Haiming Liu, Changkyu Kim, Jaehyuk Huh, Burger, D., Keckler, S.W., Moore, C.

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A NUCA Substrate for Flexible CMP Cache Sharing von Jaehyuk Huh, J., Changkyu Kim, C., Shafi, H., Lixin Zhang, L., Burger, D., Keckler, S.W.

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Scalable hardware memory disambiguation for high-ILP processors von Sethumadhavan, S., Desikan, R., Burger, D., Moore, C.R., Keckler, S.W.

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An efficient, protected message interface von Whay Sing Lee, Dally, W.J., Keckler, S.W., Carter, N.P., Chang, A.

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How to implement effective prediction and forwarding for fusable dynamic multicore architectures von Robatmili, B., Dong Li, Esmaeilzadeh, H., Govindan, S., Smith, A., Putnam, A., Burger, D., Keckler, S. W.

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Scalable hardware memory disambiguation for high ILP processors von Sethumadhavan, S., Desikan, R., Burger, D., Moore, C.R., Keckler, S.W.

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Exploiting microarchitectural redundancy for defect tolerance von Shivakumar, P., Keckler, S. W., Moore, C. R., Burger, D.

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Exploiting criticality to reduce bottlenecks in distributed uniprocessors von Robatmili, B, Govindan, S, Burger, D, Keckler, S W

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The M-Machine multicomputer von FILLO, M, KECKLER, S. W, DALLY, W. J, CARTER, N. P, CHANG, A, GUREVICH, Y, LEE, W. S

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A design space evaluation of grid processor architectures von Nagarajan, Ramadass, Sankaralingam, Karthikeyan, Burger, Doug, Keckler, Stephen W.

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Clock rate versus IPC: the end of the road for conventional microarchitectures von Agarwal, Vikas, Hrishikesh, M. S., Keckler, Stephen W., Burger, Doug

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