Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs von Ran Wang, Zipeng Li, Kannan, Sukeshwar, Chakrabarty, Krishnendu

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A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits von Koneru, Abhishek, Kannan, Sukeshwar, Chakrabarty, Krishnendu

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Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits von Koneru, Abhishek, Kannan, Sukeshwar, Chakrabarty, Krishnendu

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SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors von Sadi, Mehdi, Kannan, Sukeshwar, Winemberg, LeRoy, Tehranipoor, Mark

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Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs von Chaudhuri, Arjun, Banerjee, Sanmitra, Kim, Jinwoo, Park, Heechun, Ku, Bon Woong, Kannan, Sukeshwar, Chakrabarty, Krishnendu, Lim, Sung Kyu

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Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects von Kannan, Sukeshwar, Kim, Bruce, Ahn, Byoungchul

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Chip Packaging Interaction (CPI) with Cu Pillar Flip Chip for 20 nm Silicon Technology and Beyond von Gao, Shan, Smith, Ryan Scott, Cho, Jae Kyu, Choi, Seungman, Kannan, Sukeshwar, Chua, Engchye, Geisler, Holm, Kuechenmeister, Frank

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More than Moore with Silicon Photonics Chiplets in Package (SCIP) von Raghunathan, Vivek, Kannan, Sukeshwar, Goh, Han Peng, Sharifi, Reza

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Physics-Based Low-Cost Test Technique for High Voltage LDMOS von Kannan, Sukeshwar, Kannan, Kaushal, Kim, Bruce C., Taenzler, Friedrich, Antley, Richard, Moushegian, Ken, Butler, Kenneth M., Mirizzi, Doug

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Physics Based Fault Models for Testing High-Voltage LDMOS von Kannan, S., Kim, B., Gupta, A., Taenzler, F., Antley, R., Moushegian, K.

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Development of hybrid electrical model for CNT based Through Silicon Vias von Kannan, Kaushal, Kannan, Sukeshwar, Kim, Bruce, Sang-Bock Cho

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Embedded RF Circuit Diagnostic Technique with Multi-Tone Dither Scheme von Kannan, Sukeshwar, Kim, Bruce, Srinivasan, Ganesh, Taenzlar, Friedrich, Antley, Richard, Force, Craig

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Development of Carbon Nanotube Based Through-Silicon Vias von Kim, Bruce C, Kannan, Sukeshwar, Gupta, Anurag, Mohammed, Falah, Ahn, Byoungchul

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Analysis of carbon nanotube based Through Silicon Vias von Kannan, Sukeshwar, Gupta, Anurag, Kim, Bruce C, Mohammed, Falah, Byoungchul Ahn

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Analysis of CNT based 3D TSV for emerging RF applications von Gupta, A., Kim, B. C., Kannan, S., Evana, S. S., Li Li

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Analysis of propagation delay in 3 - D stacked DRAM von Kannan, Sukeshwar, Kim, Bruce, Cho, Sang-Bock, Ahn, Byoungchul

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Automatic diagnostic tool for Analog-Mixed Signal and RF load boards von Kannan, S., Kim, B.C.

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Modeling and characterization of CNT-based TSV for high frequency applications von Kannan, Sukeshwar, Kim, Bruce, Gupta, Anurag, Noh, Seok-Ho, Li, Li, Cho, Sang-Bock

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System-on-Chip Integrated MEMS Packages for RF LNA Testing and Self-Calibration von KIM, Bruce C, KANNAN, Sukeshwar, SHRAVAN EVANA, Sai, NOH, Seok-Ho

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Development of Carbon Nanotube Based Through-Silicon Vias von Kim, Bruce C, Kannan, Sukeshwar, Gupta, Anurag, Mohammed, Falah, Ahn, Byoungchul

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