Predicting Protein–Ligand Docking Structure with Graph Neural Network von Jiang, Huaipan, Wang, Jian, Cong, Weilin, Huang, Yihe, Ramezani, Morteza, Sarma, Anup, Dokholyan, Nikolay V., Mahdavi, Mehrdad, Kandemir, Mahmut T.

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Affine Modeling of Program Traces von Rodriguez, Gabriel, Kandemir, Mahmut T., Tourino, Juan

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GPU-Accelerated Flexible Molecular Docking von Fan, Mengran, Wang, Jian, Jiang, Huaipan, Feng, Yilin, Mahdavi, Mehrdad, Madduri, Kamesh, Kandemir, Mahmut T, Dokholyan, Nikolay V

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Guiding Conventional Protein–Ligand Docking Software with Convolutional Neural Networks von Jiang, Huaipan, Fan, Mengran, Wang, Jian, Sarma, Anup, Mohanty, Shruti, Dokholyan, Nikolay V, Mahdavi, Mehrdad, Kandemir, Mahmut T

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Performance and Power-Efficient Design of Dense Non-Volatile Cache in CMPs von Jadidi, Amin, Arjomand, Mohammad, Kandemir, Mahmut T., Das, Chita R.

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HL-PCM: MLC PCM Main Memory with Accelerated Read von Arjomand, Mohammad, Jadidi, Amin, Kandemir, Mahmut T., Sivasubramaniam, Anand, Das, Chita R.

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On the Detection of Clones in Sensor Networks Using Random Key Predistribution von Brooks, R., Govindaraju, P.Y., Pirretti, M., Vijaykrishnan, N., Kandemir, M.T.

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Steep-Slope Devices: From Dark to Dim Silicon von Swaminathan, Karthik, Kultursay, Emre, Saripalli, Vinay, Narayanan, Vijaykrishnan, Kandemir, Mahmut T., Datta, Suman

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Optimization of Intercache Traffic Entanglement in Tagless Caches With Tiling Opportunities von Swamy Saranam Chongala, S. R., George, Sumitha, Govindarajan, Hariram Thirucherai, Kotra, Jagadish, Mutyam, Madhu, Sampson, John, Kandemir, Mahmut T., Narayanan, Vijaykrishnan

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Thorough Characterization and Analysis of Large Transformer Model Training At-Scale von Cheng, Scott, Lin, Jun-Liang, Emani, Murali, Raskar, Siddhisanket, Foreman, Sam, Xie, Zhen, Vishwanath, Venkatram, Kandemir, Mahmut Taylan

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Cache Hierarchy-Aware Query Mapping on Emerging Multicore Architectures von Ozturk, Ozcan, Orhan, Umut, Wei Ding, Yedlapalli, Praveen, Kandemir, Mahmut Taylan

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Network and Parallel Computing: 14th IFIP WG 10.3 International Conference, NPC 2017, Hefei, China, October 20-21, 2017, Proceedings von Shi, Xuanhua, An, Hong, Wang, Chao, Kandemir, Mahmut, Jin, Hai

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Volatile STT-RAM Scratchpad Design and Data Allocation for Low Energy von Rodríguez, Gabriel, Touriño, Juan, Kandemir, Mahmut T.

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Evaluating STT-RAM as an energy-efficient main memory alternative von Kultursay, Emre, Kandemir, Mahmut, Sivasubramaniam, Anand, Mutlu, Onur

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Improved cache utilization and preconditioner efficiency through use of a space-filling curve mesh element- and vertex-reordering technique von Sastry, Shankar P., Kultursay, Emre, Shontz, Suzanne M., Kandemir, Mahmut T.

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The Sleep Deprivation Attack in Sensor Networks: Analysis and Methods of Defense von Pirretti, Matthew, Zhu, Sencun, Vijaykrishnan, N., McDaniel, Patrick, Kandemir, Mahmut, Brooks, Richard

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Memory Partitioning in the Limit von Kültürsay, Emre, Ebcioğlu, Kemal, Küçük, Gürhan, Kandemir, Mahmut T.

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NSF-CSSI-Talk: Re-engineering Galaxy for Performance, Scalability and Energy Efficiency von Kandemir, Mahmut

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CaSym: Cache Aware Symbolic Execution for Side Channel Detection and Mitigation von Brotzman, Robert, Liu, Shen, Zhang, Danfeng, Tan, Gang, Kandemir, Mahmut

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Architecture-Aware Approximate Computing von Karakoy, Mustafa, Kislal, Orhan, Tang, Xulong, Kandemir, Mahmut Taylan, Arunachalam, Meenakshi

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