Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph von Hosseinabady, M., Kakoee, M. R., Mathew, J., Pradhan, D. K.

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At-Speed Distributed Functional Testing to Detect Logic and Delay Faults in NoCs von Kakoee, Mohammad Reza, Bertacco, Valeria, Benini, Luca

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Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators von Dehyadegari, Masoud, Marongiu, Andrea, Kakoee, Mohammad Reza, Mohammadi, Siamak, Yazdani, Naser, Benini, Luca

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Robust Near-Threshold Design With Fine-Grained Performance Tunability von Kakoee, M. R., Benini, L.

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Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters von Kakoee, M. R., Loi, I., Benini, L.

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Fine-Grained Power and Body-Bias Control for Near-Threshold Deep Sub-Micron CMOS Circuits von Kakoee, M. R., Benini, L.

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A resilient architecture for low latency communication in shared-L1 processor clusters von Kakoee, Mohammad Reza, Loi, Igor, Benini, Luca

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A resilient architecture for low latency communication in shared-L1 processor clusters von Kakoee, M. R., Loi, I., Benini, L.

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Reliable network-on-chip based on generalized de Bruijn graph von Hosseinabady, M., Kakoee, M.R., Mathew, J., Pradhan, D.K.

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Automatic synthesis of near-threshold circuits with fine-grained performance tunability von Kakoee, Mohammad Reza, Sathanur, Ashoka, Pullini, Antonio, Huisken, Jos, Benini, Luca

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Graph based test case generation for TLM functional verification von Kakoee, Mohammad Reza, Neishaburi, M.H., Mohammadi, Siamak

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A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services von Neishaburi, M.H., Kakoee, M.R., Daneshtalab, M., Safari, S., Navabi, Z.

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A distributed and topology-agnostic approach for on-line NoC testing von Kakoee, Mohammad Reza, Bertacco, Valeria, Benini, Luca

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SYSTEM AND METHOD FOR ONLINE FUNCTIONAL TESTING FOR ERROR-CORRECTING CODE FUNCTION von MAHURIN, Eric, VENKUMAHANTI, Suresh Kumar, CHUN, Dexter, GULATI, Rahul, KAKOEE, Mohammad Reza

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De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs von Hosseinabady, M., Kakoee, M.R., Mathew, J., Pradhan, D.K.

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MULTI-DOMAIN HETEROGENEOUS PROCESS-VOLTAGE-TEMPERATURE TRACKING FOR INTEGRATED CIRCUIT POWER REDUCTION von IBRAHIMOVIC, JASMIN SMAILA, KAKOEE, MOHAMMAD REZA, HU, SHIH-HSIN JASON

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A New Approach for Design and Verification of Transaction Level Models von Kakoee, Mohammad Reza, Shojaei, Hamid, Ghasemzadeh, Hassan, Sirjani, Marjan, Navabi, Zainalabedin

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Row-based FBB: A design-time optimization for post-silicon tunable circuits von Kakoee, Mohammad Reza, Sathanur, Ashoka, Pullini, Antonio, Benini, Luca

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Error correcting code testing von Bhuyan, Pranjal, Gulati, Rahul, Jain, Palkesh, Kakoee, Mohammad Reza

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DYNAMICALLY ADAPTIVE VOLTAGE-FREQUENCY GUARDBAND CONTROL CIRCUIT von BOWMAN, Keith Alan, HO, Lam, HU, Shih-Hsin Jason, KANNAN, Saravana Krishnan, TOOSIZADEH, Navid, KAKOEE, Mohammad Reza

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