Low Leakage and High Performance tag Comparator Implemented in 180nm CMOS Technology von Koshy, Lidiya Mariam, Chandran, G. Jyothish

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Design and Analysis of 8 Bit Parallel Prefix Comparators Using Constant Delay Logic von George, Amy Mariam, Chandran, G. Jyothish

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Implementation of an area efficient data converter with increased effective number of bits von Jyothish, Chandran G., John, S. K.

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Low Leakage and High Performance tag Comparator Implemented in 180 nm CMOS Technology von Koshy, Lidiya Mariam, Chandran, G. Jyothish

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DESIGN OF HIGH PERFORMANCE DOUBLE TAIL COMPARATOR von P M, Saranya, G, Jyothish Chandran, K S, Shilpa

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DESIGN AND ANALYSIS OF AN EFFICIENT FULL ADDER USING SYSTEMATIC CELL DESIGN METHODOLOGY von G, Jyothish Chandran, George, Anila Susan, Raj, Anu

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Digital Health Infrastructure von Baby, Bijin Elsa, Chandran, G. Jyothish

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