NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory von Xiangyu Dong, Cong Xu, Yuan Xie, Jouppi, N. P.

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Photonic Architectures for High-Performance Data Centers von Beausoleil, R. G., McLaren, M., Jouppi, N. P.

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Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories von Yoon, Hanbin, Meza, Justin, Muralimanohar, Naveen, Jouppi, Norman P., Mutlu, Onur

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Heterogeneous chip multiprocessors von Kumar, R., Tullsen, D.M., Jouppi, N.P., Ranganathan, P.

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Optical Interconnects for High-Performance Computing Systems von Tan, M. R. T., McLaren, M., Jouppi, N. P.

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FREE-p: Protecting non-volatile memory against both hard and soft errors von Doe Hyun Yoon, Muralimanohar, N, Jichuan Chang, Ranganathan, P, Jouppi, N P, Erez, M

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Architecting Efficient Interconnects for Large Caches with CACTI 6.0 von Muralimanohar, N., Balasubramonian, R., Jouppi, N.P.

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Corona: System Implications of Emerging Nanophotonic Technology von Vantrease, Dana, Schreiber, Robert, Monchiero, Matteo, McLaren, Moray, Jouppi, Norman P., Fiorentino, Marco, Davis, Al, Binkert, Nathan, Beausoleil, Raymond G., Ahn, Jung Ho

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CACTI: an enhanced cache access and cycle time model von Wilton, S.J.E., Jouppi, N.P.

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Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance von Kumar, Rakesh, Tullsen, Dean M., Ranganathan, Parthasarathy, Jouppi, Norman P., Farkas, Keith I.

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Understanding the trade-offs in multi-level cell ReRAM memory design von Xu, Cong, Niu, Dimin, Muralimanohar, Naveen, Jouppi, Norman P., Xie, Yuan

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Complexity-effective superscalar processors von Palacharla, Subbarao, Jouppi, Norman P., Smith, J. E.

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Isolation in Commodity Multicore Processors von Aggarwal, N., Ranganathan, P., Jouppi, N.P., Smith, J.E.

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Devices and architectures for photonic chip-scale integration von Ahn, J., Fiorentino, M., Beausoleil, R. G., Binkert, N., Davis, A., Fattal, D., Jouppi, N. P., McLaren, M., Santori, C. M., Schreiber, R. S., Spillane, S. M., Vantrease, D., Xu, Q.

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A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies von Thoziyoor, Shyamkumar, Ahn, Jung Ho, Monchiero, Matteo, Brockman, Jay B., Jouppi, Norman P.

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A High-Speed Optical Multidrop Bus for Computer Interconnections von Tan, M.R.T., Rosenberg, P., Jong-Souk Yeo, McLaren, M., Mathai, S., Morris, T., Huei Pei Kuo, Straznicky, J., Jouppi, N.P., Shih-Yuan Wang

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Hybrid checkpointing using emerging nonvolatile memories for future exascale systems von Dong, Xiangyu, Xie, Yuan, Muralimanohar, Naveen, Jouppi, Norman P.

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Motivation for and Evaluation of the First Tensor Processing Unit von Jouppi, Norman, Young, Cliff, Patil, Nishant, Patterson, David

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Computer technology and architecture: an evolving interaction von Hennessy, J.L., Jouppi, N.P.

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Endurance-aware cache line management for non-volatile caches von Wang, Jue, Dong, Xiangyu, Xie, Yuan, Jouppi, Norman P.

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