Characteristics of the full CMOS SRAM cell using body-tied TG MOSFETs (bulk FinFETs) von Tai-Su Park, Hye Jin Cho, Jeong Dong Choe, Sang Yeon Han, Donggun Park, Kinam Kim, Yoon, E., Jong-Ho Lee

Volltext

Synchronous Pulse Plasma Operation upon Source and Bias Radio Frequencys for Inductively Coupled Plasma for Highly Reliable Gate Etching Technology von Tokashiki, Ken, Cho, Hong, Banna, Samer, Lee, Jeong-Yun, Shin, Kyoungsub, Todorow, Valentin, Kim, Woo-Seok, Bai, KeunHee, Joo, Sukho, Choe, Jeong-Dong, Ramaswamy, Kartik, Agarwal, Ankur, Rauf, Shahid, Collins, Ken, Choi, SangJun, Cho, Han, Kim, Hyun Joong, Lee, Changhun, Lymberopoulos, Dimitris, Yoon, Junho, Han, Woosung, Moon, Joo-Tae

Volltext

Characteristics of body-tied triple-gate pMOSFETs von Tai-Su Park, Hye Jin Cho, Jeong Dong Choe, Il Hwan Cho, Donggun Park, Yoon, E., Jong Ho Lee

Volltext

Twin SONOS memory with 30-nm storage nodes under a merged gate fabricated with inverted sidewall and damascene process von Yong Kyu Lee, Ki Whan Song, Jae Woong Hyun, Jong Duk Lee, Byung-Gook Park, Sung Taeg Kang, Jeong Dong Choe, Sang Yeon Han, Jeong Nam Han, Sung Woo Lee, Kwon, O.I., Chung, C., Donggun Park, Kinam Kim

Volltext

Fin-Type Field-Effect Transistor NAND Flash with Nitride/Silicon Nanocrystal/Nitride Hybrid Trap Layer von Choe, Jeong-Dong, Lee, Se-Hoon, Lee, Jong Jin, Cho, Eun Suk, Ahn, Youngjoon, Choi, Byoung Yong, Sung, Suk Kang, No, Jintae, Chung, Ilsub, Park, Kyucharn, Park, Donggun

Volltext

A 22-nm damascene-gate MOSFET fabrication with 0.9-nm EOT and local channel implantation von Jeong-Dong Choe, Chang-Sub Lee, Sung-Ho Kim, Sung-Min Kim, Shin-Ae Lee, Ju-Won Lee, Shin, Y.-G., Donggun Park, Kinam Kim

Volltext

A partially insulated field-effect transistor (PiFET) as a candidate for scaled transistors von Yeo, K.H., Oh, C.W., Kim, S.M., Kim, M.S., Lee, C.S., Lee, S.Y., Han, S.Y., Yoon, E.J., Cho, H.J., Lee, D.Y., Yoon, B.M., Rhee, H.S., Lee, B.C., Choe, J.D., Chung, I., Park, D., Kim, K.

Volltext

Threshold Voltage Behavior of Body-Tied FinFET (OMEGA MOSFET) with Respect to Ion Implantation Conditions von Park, Tai-su, Cho, Hye Jin, Choe, Jeong Dong, Park, Donggun, Yoon, Euijoon, Lee, Jong-Ho

Volltext

Vertical Structure NAND flash array integration with paired FinFET multi-bit scheme for high-density NAND flash memory application von June-Mo Koo, Tae-Eung Yoon, Taehee Lee, Sungjae Byun, Young-Gu Jin, Wonjoo Kim, Sukpil Kim, Jongbong Park, Junseok Cho, Jeong-Dong Choe, Choong-Ho Lee, Jong Jin Lee, Je-Woo Han, Yunseung Kang, Sangjun Park, Byoungho Kwon, Yong-Ju Jung, Inkyoung Yoo, Yoondong Park

Volltext

Hybrid ALD-SiN/Si-nanocrystals/ALD-SiN FinFET device with large P/E window for MLC NAND Flash memory application von Jeong-Dong Choe, Se-Hoon Lee, Young Joon Ahn, Donghoon Jang, Young-Bae Yoon, Jong Jin Lee, Ilsub Chung, Kyucharn Park, Donggun Park

Volltext

Lateral integration of partially insulated and bulk MOSFETs using partial SOI process von Sung Hwan Kim, Chang Woo Oh, Kyoung Hwan Yeo, Dong Uk Choi, Min Sang Kim, Sung Min Kim, Jeong Dong Choe, Jeongnam Han, Young-Pil Kim, Dong-Won Kim, Donggun Park, Byung-Il Ryu

Volltext

Fin width scaling criteria of body-tied FinFET in sub-50 nm regime von Hye Jin Cho, Jeong Dong Choe, Ming Li, Jin Young Kim, Sung Hoon Chung, Chang Woo Oh, Eun-Jung Yoon, Dong-Won Kim, Donggun Park, Kinam Kim

Volltext

Fabrication and characteristics of P -channel silicon-oxide-nitride-oxide-silicon flash memory device based on bulk fin shaped field effect transistor structure von Cho, Il Hwan, Park, Tai-Su, Choe, Jeong Dong, Cho, Hye Jin, Park, Donggun, Shin, Hyungcheol, Park, Byung-Gook, Lee, Jong Duk, Lee, Jong-Ho

Volltext

Improved Bake Retention Characteristic of Recessed Charge Trap Flash (RCTF) von Lee, Se Hoon, Kim, Woo-Jung, Yoon, Young-Bae, Park, Kyucharn, Lee, Jong Jin, Jang, Donghoon, Choe, Jeong-Dong, Kim, Taeyong, Cho, Eun Suk, Park, Se Joon, Ahn, Young Joon, Hwang, Won

Volltext

Improved post-cycling characteristic of FinFET NAND Flash von Se Hoon Lee, Jong Jin Lee, Jeong-Dong Choe, Eun Suk Cho, Young Joon Ahn, Won Hwang, Taeyong Kim, Woo-Jung Kim, Young-Bae Yoon, Donghoon Jang, Jongryeol Yoo, Dongdae Kim, Kyucharn Park, Donggun Park, Byung-Il Ryu

Volltext

The Vth controllability of 5nm body-tied CMOS FinFET von Hye Jin Cho, Jeong Dong Choe, Jeongnam Han, Dongchan Kim, Heungsik Park, Doohoon Goo, Ming Li, Chang Woo Oh, Dong-Won Kim, Tae Yong Kim, Choong-Ho Lee, Donggun Park, Kinam Kim, Byung-Il Ryu

Volltext

Transistor test structures for leakage current analysis of partial SOI von KYOUNG HWAN YEO, CHANG WOO OH, KIM, Dong-Won, PARK, Donggun, KIM, Kinam, KIM, Sung-Min, KIM, Min-Sang, LEE, Sung-Young, MING LI, CHO, Hye-Jin, YOON, Eun-Jung, KIM, Sung-Hwan, CHOE, Jeong-Dong

Volltext bestellen

Partially-insulated MOSFET (PiFET) and Its Application to DRAM Cell Transistor von Chang Woo Oh, Sung Hwan Kim, Kyoung Hwan Yeo, Sung Min Kim, Min Sang Kim, Jeong-Dong Choe, Dong-Won Kim, Donggun Park

Volltext

SONOS-Type FinFET Device Using P+ Poly-Si Gate and High-k Blocking Dielectric Integrated on Cell Array and GSL/SSL for Multi-Gigabit NAND Flash Memory von Sung, S.-K., Lee, S.-H., Choi, B., Lee, J., Choe, J.-D., Cho, E., Ahn, Y., Choi, D., Lee, C.-H., Kim, D., Lee, Y.-S., Kim, S., Park, D., Ryu, B.-I.

Volltext

Trap Layer Engineered FinFET NAND Flash with Enhanced Memory Window von Ahn, Y., Choe, J.-D., Lee, J., Choi, D., Cho, E., Choi, B., Lee, S.-H., Sung, S.-K., Lee, C.-H., Cheong, S., Lee, D., Kim, S., Park, D., Ryu, B.-I.

Volltext