The CMS Fast Beam Condition Monitor for HL-LHC von Auzinger, G., Bakhshiansohi, H., Dabrowski, A., Delannoy, A.G., Dierlamm, A., Dragicevic, M., Gholami, A., Gomez, G., Guthoff, M., Haranko, M., Homna, A., Jenihhin, M., Kaplon, J., Karacheban, O., Korcsmáros, B., Liu, W.H., Lokhovitskiy, A., Loos, R., Mallows, S., Michel, J., Myronenko, V., Pásztor, G., Pari, M., Schwandt, J., Sedghi, M., Shevelev, A., Shibin, K., Steinbrueck, G., Stickland, D., Ujvari, B., Wegrzyn, G.J.

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A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks von Ahmadilivani, Mohammad Hasan, Taheri, Mahdi, Raik, Jaan, Daneshtalab, Masoud, Jenihhin, Maksim

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Test time minimization for hybrid BIST of core-based systems von Jervan, Eles, Peng, Ubar, Jenihhin

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Hybrid BIST time minimization for core-based systems with STUMPS architecture von Jervan, G., Eles, P., Peng, Z., Ubar, R., Jenihhin, M.

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Optimised AES with RISC-V Vector Extensions von Rizi, Mahnaz Namazi, Zidaric, Nusa, Batina, Lejla, Mentens, Nele

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Hardware Acceleration of FHEW von Bertels, Jonas, Van Beirendonck, Michiel, Turan, Furkan, Verbauwhede, Ingrid

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Application of high-level Decision Diagrams for simulation-based Verification Tasks von Jenihhin, M, Raik, J, Chepurov, A, Ubar, R

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Test Time Minimization for Hybrid BIST of Core-Based Systems von Jervan, Gert, Eles, Petru, Peng, Zebo, Ubar, Raimund, Jenihhin, Maksim

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Electronics design and testing of the CMS Fast Beam Condition Monitor for HL-LHC von Shibin, K, Auzinger, G, Bakhshiansohi, H, Dabrowski, A, Dierlamm, A, Dragicevic, M, Gholami, A, Gomez, G, Guthoff, M, Haranko, M, Homna, A, Jenihhin, M, Kaplon, J, Karacheban, O, Korcsmáros, B, Lokhovitskiy, A, Loos, R, Mallows, S, Michel, J, Myronenko, V, Pásztor, G, Schwandt, J, Sedghi, M, Shevelev, A, Steinbrueck, G, Stickland, D, Wegrzyn, G. J

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The CMS Fast Beam Condition Monitor for HL-LHC von Auzinger, G, Bakhshiansohi, H, Dabrowski, A, Delannoy, A. G, Dierlamm, A, Dragicevic, M, Gholami, A, Gomez, G, Guthoff, M, Haranko, M, Homna, A, Jenihhin, M, Kaplon, J, Karacheban, O, Korcsmáros, B, Liu, W. H, Lokhovitskiy, A, Loos, R, Mallows, S, Michel, J, Myronenko, V, Pásztor, G, Pari, M, Schwandt, J, Sedghi, M, Shevelev, A, Shibin, K, Steinbrueck, G, Stickland, D, Ujvari, B, Wegrzyn, G. J

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New categories of Safe Faults in a processor-based Embedded System von Gursoy, C C, Jenihhin, M, Oyeniran, A S, Piumatti, D, Raik, J, M Sonza Reorda, Ubar, R

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Hybrid BIST optimization for core-based systems with test pattern broadcasting von Ubar, R., Jenihhin, M., Jervan, G., Zebo Peng

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Electronics design and testing of the CMS Fast Beam Condition Monitor for HL-LHC von Shibin, K, Auzinger, G, Bakhshiansohi, H, Dabrowski, A, Dierlamm, A, Dragicevic, M, Gholami, A, Gomez, G, Guthoff, M, Haranko, M, Homna, A, Jenihhin, M, Kaplon, J, Karacheban, O, Korcsmáros, B, Lokhovitskiy, A, Loos, R, Mallows, S, Michel, J, Myronenko, V, Pásztor, G, Schwandt, J, Sedghi, M, Shevelev, A, Steinbrueck, G, Stickland, D, Wegrzyn, G J

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The CMS Fast Beam Condition Monitor for HL-LHC von Auzinger, G, Bakhshiansohi, H, Dabrowski, A, Delannoy, A G, Dierlamm, A, Dragicevic, M, Gholami, A, Gomez, G, Guthoff, M, Haranko, M, Homna, A, Jenihhin, M, Kaplon, J, Karacheban, O, Korcsmáros, B, Liu, W H, Lokhovitskiy, A, Loos, R, Mallows, S, Michel, J, Myronenko, V, Pásztor, G, Pari, M, Schwandt, J, Sedghi, M, Shevelev, A, Shibin, K, Steinbrueck, G, Stickland, D, Ujvari, B, Wegrzyn, G J

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Extensible open-source framework for translating RTL VHDL IP cores to SystemC von Syed, S. A., Jenihhin, M., Raik, J.

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Combining dynamic slicing and mutation operators for ESL correction von Repinski, U., Hantson, H., Jenihhin, M., Raik, J., Ubar, R., Di Guglielmo, G., Pravadelli, G., Fummi, F.

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Improving the iterative power of resynthesis von Fiser, P., Schmidt, J.

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Automated test bench generation for high-level synthesis flow ABELITE von Viilukas, T., Jenihhin, M., Raik, J., Ubar, R., Baranov, S.

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Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits von Raik, J., Rannaste, A., Jenihhin, M., Viilukas, T., Ubar, R., Fujiwara, H.

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High-level design error diagnosis using backtrace on decision diagrams von Raik, J, Repinski, U, Ubar, R, Jenihhin, M, Chepurov, A

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