High level programming abstractions for leveraging hierarchical memories with micro-core architectures von Jamieson, Maurice, Brown, Nick

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Enabling high performance dynamic language programming for micro-core architectures von Jamieson, Maurice

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Performance of the Vipera Framework for DSLs on Micro-Core Architectures von Jamieson, Maurice, Brown, Nick

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Performance characterisation of the 64-core SG2042 RISC-V CPU for HPC von Brown, Nick, Jamieson, Maurice

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Performance of the Vipera framework for DSLs on micro-core architectures von Jamieson, Maurice, Brown, Nick

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Backporting RISC-V Vector Assembly von Lee, Joseph K. L., Jamieson, Maurice, Brown, Nick

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Test-Driving RISC-V Vector Hardware for HPC von Lee, Joseph K. L., Jamieson, Maurice, Brown, Nick, Jesus, Ricardo

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Compact Native Code Generation for Dynamic Languages on Micro-core Architectures von Jamieson, Maurice, Brown, Nick

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Benchmarking micro-core architectures for detecting disasters at the edge von Jamieson, Maurice, Brown, Nick

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High level programming abstractions for leveraging hierarchical memories with micro-core architectures von Jamieson, Maurice, Brown, Nick

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Performance characterisation of the 64-core SG2042 RISC-V CPU for HPC von Brown, Nick, Jamieson, Maurice

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Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU von Brown, Nick, Jamieson, Maurice, Lee, Joseph, Wang, Paul

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Fortran performance optimisation and auto-parallelisation by leveraging MLIR-based domain specific abstractions in Flang von Brown, Nick, Jamieson, Maurice, Lydike, Anton, Bauer, Emilien, Grosser, Tobias

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Performance of the Vipera framework for DSLs on micro-core architectures von Jamieson, Maurice, Brown, Nick

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Experiences of running an HPC RISC-V testbed von Brown, Nick, Jamieson, Maurice, Lee, Joseph K. L

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Test-driving RISC-V Vector hardware for HPC von Lee, Joseph K. L, Jamieson, Maurice, Brown, Nick, Jesus, Ricardo

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Backporting RISC-V Vector assembly von Lee, Joseph K. L, Jamieson, Maurice, Brown, Nick

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Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA von Rodriguez-Canal, Gabriel, Brown, Nick, Jamieson, Maurice, Bauer, Emilien, Lydike, Anton, Grosser, Tobias

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Compact Native Code Generation for Dynamic Languages on Micro-core Architectures von Jamieson, Maurice, Brown, Nick

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A shared compilation stack for distributed-memory parallelism in stencil DSLs von Bisbas, George, Lydike, Anton, Bauer, Emilien, Brown, Nick, Fehr, Mathieu, Mitchell, Lawrence, Rodriguez-Canal, Gabriel, Jamieson, Maurice, Kelly, Paul H. J, Steuwer, Michel, Grosser, Tobias

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