Top Picks from the 2016 Computer Architecture Conferences von Jaleel, Aamer, Qureshi, Moinuddin

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DUCATI: High-performance Address Translation by Extending TLB Reach of GPU-accelerated Systems von Jaleel, Aamer, Ebrahimi, Eiman, Duncan, Sam

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Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks von Domnitser, Leonid, Jaleel, Aamer, Loew, Jason, Abu-Ghazaleh, Nael, Ponomarev, Dmitry

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CoLT: Coalesced Large-Reach TLBs von Pham, B., Vaidyanathan, V., Jaleel, A., Bhattacharjee, A.

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Scheduling heterogeneous multi-cores through performance impact estimation (PIE) von Van Craeynest, K., Jaleel, A., Eeckhout, L., Narvaez, P., Emer, J.

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Beyond the socket: NUMA-aware GPUs von Ugljesa, Milic, Villa, Oreste, Bolotin, Evgeny, Arunkumar, Akhil, Ebrahimi, Eiman, Jaleel, Aamer, Ramirez, Alex, Nellans, David

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Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing von Pellauer, Michael, Clemons, Jason, Balaji, Vignesh, Crago, Neal, Jaleel, Aamer, Lee, Donghyuk, O’Connor, Mike, Parashar, Angshuman, Treichler, Sean, Tsai, Po-An, Keckler, Stephen W., Emer, Joel S.

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cuCatch: A Debugging Tool for Efficiently Catching Memory Safety Violations in CUDA Applications von Tarek Ibn Ziad, Mohamed, Damani, Sana, Jaleel, Aamer, Keckler, Stephen W., Stephenson, Mark

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Mind The Power Holes: Sifting Operating Points in Power-Limited Heterogeneous Multicores von Adileh, Almutaz, Eyerman, Stijn, Jaleel, Aamer, Eeckhout, Lieven

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Analyzing Parallel Programs with PIN von Bach, M., Charney, M., Cohn, R., Demikhovsky, E., Devor, T., Hazelwood, K., Jaleel, A., Chi-Keung Luk, Lyons, G., Patil, H., Tal, A.

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Maximizing Heterogeneous Processor Performance Under Power Constraints von Adileh, Almutaz, Eyerman, Stijn, Jaleel, Aamer, Eeckhout, Lieven

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Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures von Ozdal, Muhammet Mustafa, Jaleel, Aamer, Narvaez, Paolo, Burns, Steven, Srinivasa, Ganapati

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Efficient Spatial Processing Element Control via Triggered Instructions von Parashar, Angshuman, Pellauer, Michael, Adler, Michael, Ahsan, Bushra, Crago, Neal, Lustig, Daniel, Pavlov, Vladimir, Zhai, Antonia, Gambhir, Mohit, Jaleel, Aamer, Allmon, Randy, Rayess, Rachid, Maresh, Stephen, Emer, Joel

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Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures von Pellauer, Michael, Parashar, Angshuman, Adler, Michael, Ahsan, Bushra, Allmon, Randy, Crago, Neal, Fleming, Kermin, Gambhir, Mohit, Jaleel, Aamer, Krishna, Tushar, Lustig, Daniel, Maresh, Stephen, Pavlov, Vladimir, Rayess, Rachid, Zhai, Antonia, Emer, Joel

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ImPress: Securing DRAM Against Data-Disturbance Errors via Implicit Row-Press Mitigation von Qureshi, Moinuddin, Saxena, Anish, Jaleel, Aamer

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MINT: Securely Mitigating Rowhammer with a Minimalist In-DRAM Tracker von Qureshi, Moinuddin, Qazi, Salman, Jaleel, Aamer

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Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies von Jaleel, A, Borch, E, Bhandaru, M, Steely, Simon C, Emer, J

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Probabilistic Tracker Management Policies for Low-Cost and Scalable Rowhammer Mitigation von Jaleel, Aamer, Keckler, Stephen W, Saileshwar, Gururaj

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PROBABILISTIC TRACKER MANAGEMENT FOR MEMORY ATTACK MITIGATION von Jaleel, Aamer, Saileshwar, Gururaj

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The gradient-based cache partitioning algorithm von Hasenplaugh, William, Ahuja, Pritpal S., Jaleel, Aamer, Steely Jr, Simon, Emer, Joel

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