XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks von Yin, Shihui, Jiang, Zhewei, Seo, Jae-Sun, Seok, Mingoo

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Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA von Ma, Yufei, Cao, Yu, Vrudhula, Sarma, Seo, Jae-sun

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High-Throughput In-Memory Computing for Binary Deep Neural Networks With Monolithically Integrated RRAM and 90-nm CMOS von Yin, Shihui, Sun, Xiaoyu, Yu, Shimeng, Seo, Jae-Sun

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C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism von Jiang, Zhewei, Yin, Shihui, Seo, Jae-Sun, Seok, Mingoo

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An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access von Kim, Minkyu, Seo, Jae-Sun

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Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators von Ma, Yufei, Cao, Yu, Vrudhula, Sarma, Seo, Jae-Sun

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Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM-Based Deep Learning Inference Engine von Shim, Wonbo, Luo, Yandong, Seo, Jae-Sun, Yu, Shimeng

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An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition von Kadetotad, Deepak, Yin, Shihui, Berisha, Visar, Chakrabarti, Chaitali, Seo, Jae-sun

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Performance Modeling for CNN Inference Accelerators on FPGA von Ma, Yufei, Cao, Yu, Vrudhula, Sarma, Seo, Jae-Sun

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Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks von Meng, Jian, Yang, Li, Peng, Xiaochen, Yu, Shimeng, Fan, Deliang, Seo, Jae-Sun

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PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference von Zhang, Bo, Yin, Shihui, Kim, Minkyu, Saikia, Jyotishman, Kwon, Soonwan, Myung, Sungmeen, Kim, Hyunsoo, Kim, Sang Joon, Seo, Jae-Sun, Seok, Mingoo

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Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain von Thakur, Chetan Singh, Molin, Jamal Lottier, Cauwenberghs, Gert, Indiveri, Giacomo, Kumar, Kundan, Qiao, Ning, Schemmel, Johannes, Wang, Runchun, Chicca, Elisabetta, Olson Hasler, Jennifer, Seo, Jae-Sun, Yu, Shimeng, Cao, Yu, van Schaik, André, Etienne-Cummings, Ralph

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Triple-Mode, Hybrid-Storage, Energy Harvesting Power Management Unit: Achieving High Efficiency Against Harvesting and Load Power Variabilities von Jiangyi Li, Jae-sun Seo, Kymissis, Ioannis, Mingoo Seok

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Array-Level Programming of 3-Bit per Cell Resistive Memory and Its Application for Deep Neural Network Inference von Luo, Yandong, Han, Xu, Ye, Zhilu, Barnaby, Hugh, Seo, Jae-Sun, Yu, Shimeng

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A 1.06- \mu W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring von Yin, Shihui, Kim, Minkyu, Kadetotad, Deepak, Liu, Yang, Bae, Chisung, Kim, Sang Joon, Cao, Yu, Seo, Jae-Sun

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Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks von Yin, Shihui, Jiang, Zhewei, Kim, Minkyu, Gupta, Tushar, Seok, Mingoo, Seo, Jae-Sun

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A 65-nm RRAM Compute-in-Memory Macro for Genome Processing von Zhang, Fan, Sridharan, Amitesh, He, Wangxin, Yeo, Injune, Liehr, Maximilian, Zhang, Wei, Cady, Nathaniel, Cao, Yu, Seo, Jae-Sun, Fan, Deliang

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Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning von Yin, Shihui, Kim, Yulhwa, Han, Xu, Barnaby, Hugh, Yu, Shimeng, Luo, Yandong, He, Wangxin, Sun, Xiaoyu, Kim, Jae-Joon, Seo, Jae-sun

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Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions von Basu, Arindam, Acharya, Jyotibdha, Karnik, Tanay, Liu, Huichu, Li, Hai, Seo, Jae-Sun, Song, Chang

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Specifications of Nanoscale Devices and Circuits for Neuromorphic Computational Systems von Rajendran, B., Yong Liu, Jae-sun Seo, Gopalakrishnan, K., Chang, Leland, Friedman, D. J., Ritter, M. B.

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