Motivation for and Evaluation of the First Tensor Processing Unit von Jouppi, Norman, Young, Cliff, Patil, Nishant, Patterson, David

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NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory von Xiangyu Dong, Cong Xu, Yuan Xie, Jouppi, N. P.

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The Design Process for Google's Training Chips: TPUv2 and TPUv3 von Norrie, Thomas, Patil, Nishant, Yoon, Doe Hyun, Kurian, George, Li, Sheng, Laudon, James, Young, Cliff, Jouppi, Norman, Patterson, David

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Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories von Yoon, Hanbin, Meza, Justin, Muralimanohar, Naveen, Jouppi, Norman P., Mutlu, Onur

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Photonic Architectures for High-Performance Data Centers von Beausoleil, R. G., McLaren, M., Jouppi, N. P.

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Heterogeneous chip multiprocessors von Kumar, R., Tullsen, D.M., Jouppi, N.P., Ranganathan, P.

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The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing von Li, Sheng, Ahn, Jung Ho, Strong, Richard D., Brockman, Jay B., Tullsen, Dean M., Jouppi, Norman P.

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Architecting Efficient Interconnects for Large Caches with CACTI 6.0 von Muralimanohar, N., Balasubramonian, R., Jouppi, N.P.

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Hybrid checkpointing using emerging nonvolatile memories for future exascale systems von Dong, Xiangyu, Xie, Yuan, Muralimanohar, Naveen, Jouppi, Norman P.

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Corona: System Implications of Emerging Nanophotonic Technology von Vantrease, Dana, Schreiber, Robert, Monchiero, Matteo, McLaren, Moray, Jouppi, Norman P., Fiorentino, Marco, Davis, Al, Binkert, Nathan, Beausoleil, Raymond G., Ahn, Jung Ho

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Endurance-aware cache line management for non-volatile caches von Wang, Jue, Dong, Xiangyu, Xie, Yuan, Jouppi, Norman P.

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Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance von Kumar, Rakesh, Tullsen, Dean M., Ranganathan, Parthasarathy, Jouppi, Norman P., Farkas, Keith I.

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FREE-p: Protecting non-volatile memory against both hard and soft errors von Doe Hyun Yoon, Muralimanohar, N, Jichuan Chang, Ranganathan, P, Jouppi, N P, Erez, M

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A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies von Dong, Xiangyu, Jouppi, Norman P., Xie, Yuan

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Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor von Mutlu, Onur, Belgard, Rich, Gross, Thomas R., Jouppi, Norman R., Hennessy, John L., Przybylski, Steven, Rowen, Chris, Patt, Yale N., Hwu, Wen-Mei W., Melvin, Stephen W., Shebanow, Michael C., Yeh, Tse-Yu, Wolfe, Andy

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Improving System Energy Efficiency with Memory Rank Subsetting von Ahn, Jung Ho, Jouppi, Norman P., Kozyrakis, Christos, Leverich, Jacob, Schreiber, Robert S.

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Optical high radix switch design von Binkert, N., Davis, A., Jouppi, N., McLaren, M., Muralimanohar, N., Schreiber, R., Ahn, J. H.

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Free-p: A Practical End-to-End Nonvolatile Memory Protection Mechanism von Doe Hyun Yoon, Muralimanohar, N., Jichuan Chang, Ranganathan, P., Jouppi, Norman P., Erez, M.

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Optical Interconnects for High-Performance Computing Systems von Tan, M. R. T., McLaren, M., Jouppi, N. P.

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Understanding the trade-offs in multi-level cell ReRAM memory design von Xu, Cong, Niu, Dimin, Muralimanohar, Naveen, Jouppi, Norman P., Xie, Yuan

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