Evaluation of BCB Bonded and Thinned Wafer Stacks for Three-Dimensional Integration von Kwon, Yongchai, Jindal, Anurag, Augur, Rod, Seok, Jongwon, Cale, Timothy S., Gutmann, Ronald J., Lu, Jian-Qiang

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Computed Tomography for Evaluation of Mild to Moderate Pediatric Trauma: Are We Overusing It? von Jindal, Anurag, Velmahos, George C., Rofougaran, Roya

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Assessment of Reliability of Cone-beam Computed Tomography in Skeletal and Dental Discrepancy von Khandelwal, Ashok, Raghav, Shweta, Baheti, Kamalshikha, Jindal, Anurag, Bansod, Shubhanjali, Choudhary, Amit Singh

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DATA MINING IN EDUCATION FOR STUDENTS ACADEMIC PERFORMANCE: A SYSTEMATIC REVIEW von Jindal, Anurag, Singh, Er. Williamjeet

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Inverse analysis of material removal data using a multiscale CMP model von Seok, Jongwon, Kim, Andrew T., Sukam, Cyriaque P., Jindal, Anurag, Tichy, John A., Gutmann, Ronald J., Cole, Timothy S.

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Developing CMP for Future of Memory von Jindal, Anurag, Mishra, Maneesh, Carswell, Andrew

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Endoscopic Needle Knife Sphincterotome—an Alternative for Retrieval of an Entrapped Nasogastric Tube von Kataria, Hanish, Sharma, Rajeev, Bansiwal, Rajesh, Jindal, Anurag, Attri, A. K.

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BUILT IN SELF TEST (BIST) FOR CLOCK GENERATION CIRCUITRY von CORSO SARMIENTO, Jorge Arturo, JINDAL, Anurag

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Compliance with Sequential Compression Device Prophylaxis in At-Risk Trauma Patients: A Prospective Analysis von Cornwell, Edward E., Chang, David, Velmahos, George, Jindal, Anurag, Baker, Deborah, Phillips, Judy, Bonar, James, Campbell, Kurtis

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Built in self test (BIST) for clock generation circuitry von Corso Sarmiento, Jorge Arturo, Jindal, Anurag

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BUILT IN SELF TEST (BIST) FOR CLOCK GENERATION CIRCUITRY von CORSO SARMIENTO, Jorge Arturo, JINDAL, Anurag

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BUILT IN SELF TEST (BIST) FOR CLOCK GENERATION CIRCUITRY von Corso Sarmiento, Jorge Arturo, Jindal, Anurag

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IDENTIFYING TEST COVERAGE GAPS FOR INTEGRATED CIRCUIT DESIGNS BASED ON NODE TESTABILITY AND PHYSICAL DESIGN DATA von NARULA, Kapil, JINDAL, Anurag, LIANG, Hongkun, KALYAN, Rahul

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Reset generation circuit for scan mode exit von JINDAL ANURAG

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RESET GENERATION CIRCUIT FOR SCAN MODE EXIT von JINDAL ANURAG

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METHODS OF EXPOSING CONDUCTIVE VIAS OF SEMICONDUCTOR DEVICES AND RELATED SEMICONDUCTOR DEVICES von Vasilyeva, Irina, Li, Hongqi, Jindal, Anurag

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Splenic arterial hemorrhage in pancreatitis : report of three cases von GURPREET SINGH, LOBO, D. R. N, ANURAG JINDAL, MARWAHA, R. K, KHANNA, S. K

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“Insignificant” mechanism of injury: not to be taken lightly von Velmahos, George C, Jindal, Anurag, Chan, Linda S, Murray, James A, Vassiliu, Pantelis, Berne, Thomas V, Asensio, Juan, Demetriades, Demetrios

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Structural testing of integrated circuits von Jindal Anurag, Mahajan Nipun

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IDENTIFYING TEST COVERAGE GAPS FOR INTEGRATED CIRCUIT DESIGNS BASED ON NODE TESTABILITY AND PHYSICAL DESIGN DATA von NARULA, Kapil, JINDAL, Anurag, LIANG, Hongkun, KALYAN, Rahul

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