Reduction of Process Variations for Sub-5-nm Node Fin and Nanosheet FETs Using Novel Process Scheme von Yoon, Jun-Sik, Lee, Seunghwan, Lee, Junjong, Jeong, Jinsu, Yun, Hyeok, Baek, Rock-Hyun

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Accurate Evaluation of Electro-Thermal Performance in Silicon Nanosheet Field-Effect Transistors with Schemes for Controlling Parasitic Bottom Transistors von Jeong, Jinsu, Lee, Sanguk, Baek, Rock-Hyun

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Systematic DC/AC Performance Benchmarking of Sub-7-nm Node FinFETs and Nanosheet FETs von Yoon, Jun-Sik, Jeong, Jinsu, Lee, Seunghwan, Baek, Rock-Hyun

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Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application von Jeong, Jinsu, Yoon, Jun-Sik, Lee, Seunghwan, Baek, Rock-Hyun

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Optimization of nanosheet number and width of multi-stacked nanosheet FETs for sub-7-nm node system on chip applications von Yoon, Jun-Sik, Jeong, Jinsu, Lee, Seunghwan, Baek, Rock-Hyun

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Bottom Oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node von Yoon, Jun-Sik, Jeong, Jinsu, Lee, Seunghwan, Baek, Rock-Hyun

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Punch-Through-Stopper Free Nanosheet FETs With Crescent Inner-Spacer and Isolated Source/Drain von Yoon, Jun-Sik, Jeong, Jinsu, Lee, Seunghwan, Baek, Rock-Hyun

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DC Performance Variations by Grain Boundary in Source/Drain Epitaxy of Sub-3-nm Nanosheet Field-Effect Transistors von Yoon, Jun-Sik, Jeong, Jinsu, Lee, Seunghwan, Lee, Junjong, Lee, Sanguk, Lim, Jaewan, Baek, Rock-Hyun

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Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation von Eom, Seungjoon, Yun, Hyeok, Jang, Hyundong, Cho, Kyeongrae, Lee, Seunghwan, Jeong, Jinsu, Baek, Rock‐Hyun

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Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs von Jeong, Jinsu, Yoon, Jun-Sik, Baek, Rock-Hyun

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Multi-Task Learning for Real-Time BSIM-CMG Parameter Extraction of NSFETs with Multiple Structural Variations von Lee, Seunghwan, Eom, Seungjoon, Jeong, Jinsu, Lee, Junjong, Lee, Sanguk, Yun, Hyeok, Ahn, Yonghwan, Baek, Rock-Hyun

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Sensitivity of Inner Spacer Thickness Variations for Sub-3-nm Node Silicon Nanosheet Field-Effect Transistors von Lee, Sanguk, Jeong, Jinsu, Yoon, Jun-Sik, Lee, Seunghwan, Lee, Junjong, Lim, Jaewan, Baek, Rock-Hyun

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A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs von Lee, Sanguk, Jeong, Jinsu, Kang, Bohyeon, Lee, Seunghwan, Lee, Junjong, Lim, Jaewan, Hwang, Hyeonjun, Ahn, Sungmin, Baek, Rockhyun

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Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes von Lee, Junjong, Yoon, Jun-Sik, Jeong, Jinsu, Lee, Seunghwan, Lee, Sanguk, Baek, Rock-Hyun

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Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node von Yoon, Jun-Sik, Lee, Seunghwan, Lee, Junjong, Jeong, Jinsu, Yun, Hyeok, Kang, Bohyeon, Baek, Rock-Hyun

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Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15-22 nm) Nanowire FETs with Various Channel Diameters von Lee, Seunghwan, Yoon, Jun-Sik, Lee, Junjong, Jeong, Jinsu, Yun, Hyeok, Lim, Jaewan, Lee, Sanguk, Baek, Rock-Hyun

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Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC Applications von Yun, Hyeok, Yoon, Jun-Sik, Jeong, Jinsu, Lee, Seunghwan, Choi, Hyun-Chul, Baek, Rock-Hyun

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Optimization of Asymmetries in Source/Drain Configurations and Tapered Channels for Vertical-Transport Silicon Nanosheet FETs von Jeong, Jinsu, Lee, Sanguk, Baek, Rock-Hyun

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Channel Trimming Process to Improve Electro-Thermal Characteristics for Sub-3-nm Node Si Nanosheet FETs von Lee, Sanguk, Jeong, Jinsu, Baek, Rock-Hyun

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Multi- } Strategies of 7-nm node Nanosheet FETs With Limited Nanosheet Spacing von Yoon, Jun-Sik, Jeong, Jinsu, Lee, Seunghwan, Baek, Rock-Hyun

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