A 3.0 Gsymbol/s/lane MIPI C-PHY Receiver with Adaptive Level-Dependent Equalizer for Mobile CMOS Image Sensor von Choi, Seokwon, Song, Changmin, Jang, Young-Chan

Volltext

A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber von Song, Changmin, Jung, Hoyong, Chang, Kyoungseop, Cho, Kwanglae, Yoon, Seungyong, Jang, Young-Chan

Volltext

A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization von Lee, Pil-Ho, Jang, Young-Chan

Volltext

An 11-Bit 10 MS/s SAR ADC with C–R DAC Calibration and Comparator Offset Calibration von Jung, Hoyong, Youn, Eunji, Jang, Young-Chan

Volltext

A 20-Gb/s Receiver Bridge Chip With Auto-Skew Calibration for MIPI D-PHY Interface von Lee, Pil-Ho, Jang, Young-Chan

Volltext

A 12-bit 10-MS/s Pipelined SAR ADC Sharing Flash ADC and Residue Amplifier of Multiplying DAC von Jung, Hoyong, Do, Wonkyu, Park, Cheonwi, Ko, Jaehong, Jang, Young-Chan

Volltext

A 96 dB DR Second-Order CIFF Delta-Sigma Modulator with Rail-to-Rail Input Voltage Range von Kim, Juncheol, Jeon, Neungin, Do, Wonkyu, Jung, Euihoon, Kim, Hongjin, Park, Hojin, Jang, Young-Chan

Volltext

A 10-bit 10-MS/s Asynchronous SAR ADC with Input Offset Calibration using Capacitor DAC von Son, Jisu, Jang, Young-Chan

Volltext

A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2 von Lee, Pil-Ho, Lee, Han-Yeol, Kim, Yeong-Woong, Hong, Han-Young, Jang, Young-Chan

Volltext

A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip von LEE, Pil-Ho, JANG, Young-Chan

Volltext

An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock von Lee, Pil-Ho, Lee, Han-Yeol, Lee, Hyun-Bae, Jang, Young-Chan

Volltext

A 10-bit 100-MS/s Pipelined SAR ADC with Redundancy Generation using Capacitor-based DAC and Linearity-improved Dynamic Amplifier von Lee, Han-Yeol, Youn, Eunji, Jang, Young-Chan

Volltext

A MIPI Receiver Bridge Chip Supporting 5-Gb/s/lane D-PHY and 3-Gsymbol/s/lane C-PHY von Choi, Seokwon, Lee, Pil-Ho, Han, Jin-Wook, Kim, Sang-Dong, Jang, Young-Chan

Volltext

A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display von KIM, Ho-Seong, LEE, Pil-Ho, HAN, Jin-Wook, SHIN, Seung-Hun, BAEK, Seung-Wuk, PARK, Doo-Ill, SEO, Yongkyu, JANG, Young-Chan

Volltext

A 1-kS/s 12-bit SAR ADC With Burst Conversion for Anti-Leakage Current von Son, Haewoon, Jung, Hoyong, Jang, Young-Chan

Volltext

A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators von PARK, Sang-Min, JEONG, Yeon-Ho, HWANG, Yu-Jeong, LEE, Pil-Ho, KIM, Yeong-Woong, SON, Jisu, LEE, Han-Yeol, JANG, Young-Chan

Volltext

A Self-Calibrating Per-Pin Phase Adjuster for Source Synchronous Double Data Rate Signaling in Parallel Interface von JANG, Young-Chan

Volltext

An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis von LEE, Pil-Ho, HWANG, Yu-Jeong, LEE, Han-Yeol, LEE, Hyun-Bae, JANG, Young-Chan

Volltext

A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle von LEE, Pil-Ho, LEE, Hyun Bae, JANG, Young-Chan

Volltext

A 10-bit CMOS Digital-to-Analog Converter with Compact Size for Display Applications von KIM, Mungyu, CHUNG, Hoon-Ju, JANG, Young-Chan

Volltext