Three stage low noise operational amplifier design for a 0.18 um CMOS process von Soltani, A., Yaghmaie, M., Razeghi, B., Pourandoost, R., Tous, S. I., Golmakani, A.

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Developing a new phase noise estimation technique based on time varying model von Izadpanah Tous, S., Mohamadi, E., Mousavi, M., Darvish Khalil Abadi, R., Kargaran, E., Nabovati, H.

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Voltage Drop Compensation and Congestion Management by Optimal Placement of UPFC von Saber Izadpanah Tous, Somayeh Hasanpour

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Design of 0.5V, 1.28mW CMOS UWB mixer using the body effect von Tavassoli, M., Kargaran, E., Izadpanah Tous, Saber, Nabovati, H.

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Optimal Placement of UPFC for Voltage Drop Compensation von Saber Izadpanah Tous, Elyas Salimi, Somayeh Hasanpour

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New Modeling of UPFC for Power Flow Study and Setting Parameters to Increase Voltage Level and Reduce Power Losses von Sajjad Ahmadnia, Nasir Boroomand, Saber Izadpanah Tous, Somayeh Hasanpour

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Design of Two High Performance 1-Bit CMOS Full Adder Cells von Naghizadeh, Hamid Reza, Moghadam, Mohammad Sarvghad, Tous, Saber Izadpanah, Golmakani, Abbas

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Design of Two High Performance 1-Bit CMOS Full Adder Cells von Moghadam , Mohammad Sarvghad, Naghizadeh , Hamid Reza, Tous , Saber Izadpanah, Golmakani , Abbas

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Oscillator Noise Calculation Technique Using Time Varying Model von Tous, Saber Izadpanah, Behroozi, Mahmoud, Kargaran, Ehsan, Nabovati, Hooman

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Phase noise calculation technique using time varying model von Tous, S. I., Khosravi, A., Hosseini, A., Kargaran, E., Hasanpour, S., Nabovati, H.

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